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path: root/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
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* [Power9] Exploit vector integer extend instructions when indices aren't correct.Tony Jiang2017-07-051-0/+136
* Tidy up some calls to getRegister for readability.Eric Christopher2017-06-171-5/+6
* Test commit - NFC.Lei Huang2017-06-141-1/+1
* Test commit - NFC.Kit Barton2017-06-131-1/+1
* PPCISelLowering.cpp: Fix warnings in r305214. [-Wdocumentation]NAKAMURA Takumi2017-06-131-3/+3
* [PowerPC] Match vec_revb builtins to P9 instructions.Tony Jiang2017-06-121-7/+69
* [Power9] Added support for the modsw, moduw, modsd, modud hardware instructions.Tony Jiang2017-06-121-5/+32
* [DAG] add helper to bind memop chains; NFCISanjay Patel2017-06-121-0/+1
* Sort the remaining #include lines in include/... and lib/....Chandler Carruth2017-06-061-5/+5
* [PPC] Inline expansion of memcmpZaara Syeda2017-05-311-0/+4
* [PowerPC] Fix a performance bug for PPC::XXPERMDI.Tony Jiang2017-05-311-12/+94
* [SelectionDAG] Set ISD::FPOWI to Expand by defaultCraig Topper2017-05-301-3/+0
* [PPC] Add text for assert.Tim Shen2017-05-251-1/+1
* [PPC] Fix atomics lowering in DAG lowering.Tim Shen2017-05-251-1/+3
* [PowerPC] Fix a performance bug for PPC::XXSLDWI.Tony Jiang2017-05-241-2/+86
* CodeGen: Power: Add lowering for shifts of v1i128.Kyle Butt2017-05-171-0/+15
* [PPC] Lower load acquire/seq_cst trailing fence to cmp + bne + isync.Tim Shen2017-05-161-5/+40
* [PPC] Move the combine "a << (b % (sizeof(a) * 8)) -> (PPCshl a, b)" to the b...Tim Shen2017-05-121-0/+64
* [Atomic] Remove IsStore/IsLoad in the interface, and pass the instruction ins...Tim Shen2017-05-091-7/+7
* Add extra operand to CALLSEQ_START to keep frame part set up previouslySerge Pavlov2017-05-091-12/+8
* [KnownBits] Add wrapper methods for setting and clear all bits in the underly...Craig Topper2017-05-051-1/+1
* [PowerPC] Emit VMX loads/stores for aligned ops to avoid adding swaps on LENemanja Ivanovic2017-05-021-0/+15
* Generalize the specialized flag-carrying SDNodes by moving flags into SDNode.Amara Emerson2017-05-011-5/+5
* [SelectionDAG] Use KnownBits struct in DAG's computeKnownBits and simplifyDem...Craig Topper2017-04-281-24/+20
* Move value type list from TargetRegisterClass to TargetRegisterInfoKrzysztof Parzyszek2017-04-241-2/+2
* Revert r301231: Accidentally committed stale filesKrzysztof Parzyszek2017-04-241-2/+2
* Move value type list from TargetRegisterClass to TargetRegisterInfoKrzysztof Parzyszek2017-04-241-2/+2
* [DAGCombiner] Add vector demanded elements support to computeKnownBitsForTarg...Simon Pilgrim2017-03-311-0/+1
* Kill some trailing whitespace to make some new changes a bit easier.Eric Christopher2017-03-231-12/+12
* Make library calls sensitive to regparm module flag (Fixes PR3997).Nirav Dave2017-03-181-4/+3
* Remove getArgumentList() in favor of arg_begin(), args(), etcReid Kleckner2017-03-161-1/+1
* Test commit.Hiroshi Inoue2017-03-161-1/+1
* Revert "Revert "[PowerPC][ELFv2ABI] Allocate parameter area on-demand to redu...Tim Shen2017-03-081-5/+43
* Revert "[PowerPC][ELFv2ABI] Allocate parameter area on-demand to reduce stack...Tim Shen2017-03-071-43/+5
* [PowerPC] Fix failure with STBRX when store is narrower than the bswapNemanja Ivanovic2017-03-061-2/+5
* [PPC] Fix code generation for bswap(int32) followed by store16Guozhi Wei2017-03-021-2/+10
* [PowerPC][ELFv2ABI] Allocate parameter area on-demand to reduce stack frame sizeNemanja Ivanovic2017-03-021-5/+43
* [PowerPC] Expand ISEL instruction into if-then-else sequence.Tony Jiang2017-01-161-3/+2
* Revert "[PowerPC] Expand ISEL instruction into if-then-else sequence."Tony Jiang2017-01-161-2/+3
* [PowerPC] Expand ISEL instruction into if-then-else sequence.Tony Jiang2017-01-161-3/+2
* [PowerPC] Fix some Clang-tidy modernize and Include What You Use warnings; ot...Eugene Zelenko2017-01-131-112/+233
* [PowerPC] Fix logic dealing with nop after calls (and tail-call eligibility)Hal Finkel2017-01-041-40/+39
* Revert r289638: [PowerPC] Fix logic dealing with nop after calls (and tail-ca...Chandler Carruth2016-12-161-25/+40
* [PowerPC] Fix logic dealing with nop after calls (and tail-call eligibility)Hal Finkel2016-12-141-40/+25
* [PPC] Prefer direct move on power8 if load 1 or 2 bytes to VSRGuozhi Wei2016-12-121-1/+7
* [PowerPC] Improvements for BUILD_VECTOR Vol. 2Nemanja Ivanovic2016-11-291-4/+98
* [PowerPC] Improvements for BUILD_VECTOR Vol. 2Nemanja Ivanovic2016-11-291-1/+94
* Revert https://reviews.llvm.org/rL287679Nemanja Ivanovic2016-11-291-15/+0
* [PowerPC] Improvements for BUILD_VECTOR Vol. 1Nemanja Ivanovic2016-11-291-23/+70
* [PowerPC] Emit VMX loads/stores for aligned ops to avoid adding swaps on LENemanja Ivanovic2016-11-221-0/+15
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