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author | Lei Huang <lei@ca.ibm.com> | 2017-06-14 17:25:55 +0000 |
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committer | Lei Huang <lei@ca.ibm.com> | 2017-06-14 17:25:55 +0000 |
commit | f689f69fea0048fdd6607e60d11543440723d987 (patch) | |
tree | a1e3c2ead1b8abff5f50fc36a7985e6d12ff8a3a /llvm/lib/Target/PowerPC/PPCISelLowering.cpp | |
parent | 9d24522f223c531d112126fec77b5d15506eee51 (diff) | |
download | bcm5719-llvm-f689f69fea0048fdd6607e60d11543440723d987.tar.gz bcm5719-llvm-f689f69fea0048fdd6607e60d11543440723d987.zip |
Test commit - NFC.
Modified a comment to confirm commit access functionality.
llvm-svn: 305402
Diffstat (limited to 'llvm/lib/Target/PowerPC/PPCISelLowering.cpp')
-rw-r--r-- | llvm/lib/Target/PowerPC/PPCISelLowering.cpp | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp index dc4abe44a81..662550f7a39 100644 --- a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp +++ b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp @@ -175,7 +175,7 @@ PPCTargetLowering::PPCTargetLowering(const PPCTargetMachine &TM, setOperationAction(ISD::UINT_TO_FP, MVT::i1, Custom); } - // PowerPC does not support direct load / store of condition registers + // PowerPC does not support direct load/store of condition registers. setOperationAction(ISD::LOAD, MVT::i1, Custom); setOperationAction(ISD::STORE, MVT::i1, Custom); |