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* [mips] Correct c.cond.fmt instruction definition.Simon Dardis2017-01-161-2/+105
| | | | | | | | | | | | | | | Permit explicit $fcc<X> operand in c.cond.fmt instruction. Add c.cond.fmt to the MIPS to microMIPS instruction mapping table. Check that $fcc1 - $fcc7 are unusable for MIPS-I to MIPS-III for c.cond.fmt, bc1t, bc1f. Reviewers: seanbruno, zoran.jovanovic, vkalintiris Differential Revision: https://reviews.llvm.org/D24510 llvm-svn: 292117
* Recommit: "[mips] Add rsqrt, recip for MIPS"Simon Dardis2016-10-051-0/+10
| | | | | | | | | | | Add rsqrt.[ds], recip.[ds] for MIPS. Correct the microMIPS definitions for architecture support and register usage. Reviewers: vkalintiris, zoran.jovanoic Differential Review: https://reviews.llvm.org/D24499 llvm-svn: 283334
* Revert "[mips] Add rsqrt, recip for MIPS"Simon Dardis2016-10-051-10/+0
| | | | | | | This reverts commit r282485 which contain two patches instead of one. llvm-svn: 283327
* [mips] Add rsqrt, recip for MIPSSimon Dardis2016-09-271-0/+10
| | | | | | | | | | | Add rsqrt.[ds], recip.[ds] for MIPS. Correct the microMIPS definitions for architecture support and register usage. Reviewers: vkalintiris, zoran.jovanoic Differential Review: https://reviews.llvm.org/D24499 llvm-svn: 282485
* Revert "[mips] Fix c.<cc>.<fmt> instruction definition."Simon Dardis2016-09-091-73/+5
| | | | | | | This reverts commit r281022. Mips buildbot broke, due to unhandled register class FCC. llvm-svn: 281033
* [mips] Fix c.<cc>.<fmt> instruction definition.Simon Dardis2016-09-091-5/+73
| | | | | | | | | | | | | | | As part of this effort, remove MipsFCmp nodes and use tablegen patterns rather than custom lowering through C++. Unexpectedly, this improves codesize for microMIPS as previous floating point setcc expansions would materialize 0 and 1 into GPRs before using the relevant mov[tf].[sd] instruction. Now $zero is used directly. Reviewers: dsanders, vkalintiris, zoran.jovanovic Differential Review: https://reviews.llvm.org/D23118 llvm-svn: 281022
* [mips][microMIPS] Implement CFC1, CFC2, CTC1 and CTC2 instructionsHrvoje Varga2016-08-041-5/+6
| | | | | | Differential Revision: https://reviews.llvm.org/D22347 llvm-svn: 277719
* [mips][microMIPS] Implement LDC1, SDC1, LDC2, SDC2, LWC1, SWC1, LWC2 and ↵Zlatko Buljan2016-07-111-6/+25
| | | | | | | | SWC2 instructions and add CodeGen support Differential Revision: http://reviews.llvm.org/D18824 llvm-svn: 275050
* Revert "[mips][microMIPS] Implement CFC*, CTC* and LDC* instructions"Hrvoje Varga2016-05-121-6/+1
| | | | | | This reverts commit r269176 as it caused test-suite failure. llvm-svn: 269287
* [mips][microMIPS] Implement CFC*, CTC* and LDC* instructionsHrvoje Varga2016-05-111-1/+6
| | | | | | Differential Revision: http://reviews.llvm.org/D19713 llvm-svn: 269176
* [mips][microMIPS] Revert commit r266861.Zoran Jovanovic2016-04-221-5/+1
| | | | | | Commit r266861 was the reason for failing tests in LLVM test suite. llvm-svn: 267166
* [mips][microMIPS]Implement CFC*, CTC* and LDC* instructionsHrvoje Varga2016-04-201-1/+5
| | | | | | Differential Revision: http://reviews.llvm.org/D18640 llvm-svn: 266861
* [mips][microMIPS] Implement MFC*, MFHC* and DMFC* instructionsZlatko Buljan2016-03-311-2/+2
| | | | | | Differential Revision: http://reviews.llvm.org/D17334 llvm-svn: 265002
* [mips][microMIPS] Implement MTC*, MTHC* and DMTC* instructionsHrvoje Varga2016-03-241-2/+2
| | | | | | Differential Revision: http://reviews.llvm.org/D17328 llvm-svn: 264246
* [mips][microMIPS] Implement RECIP.fmt, RINT.fmt, ROUND.L.fmt, ROUND.W.fmt, ↵Hrvoje Varga2015-12-011-2/+2
| | | | | | | | SEL.fmt, SELEQZ.fmt, SELNEQZ.fmt and CLASS.fmt Differential Revision: http://reviews.llvm.org/D13885 llvm-svn: 254405
* [mips][sched] Split IIBranch into specific instruction classes.Daniel Sanders2015-09-221-2/+2
| | | | | | | | | | | | | | | | | | | | | Summary: Almost no functional change since the InstrItinData's have been duplicated. The one functional change is to remove IIBranch from the MSA branches. The classes will be assigned to the MSA instructions as part of implementing the P5600 scheduler. II_IndirectBranchPseudo and II_ReturnPseudo can probably be removed. I've preserved the itinerary information for the corresponding pseudo instructions to avoid making a functional change to these pseudos in this patch. Reviewers: vkalintiris Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D12189 llvm-svn: 248273
* [mips][microMIPS] Implement ABS.fmt, CEIL.L.fmt, CEIL.W.fmt, FLOOR.L.fmt, ↵Zoran Jovanovic2015-09-071-9/+11
| | | | | | | | FLOOR.W.fmt, TRUNC.L.fmt, TRUNC.W.fmt, RSQRT.fmt and SQRT.fmt instructions Differential Revision: http://reviews.llvm.org/D11674 llvm-svn: 246968
* [mips] Only use FGR_{32,64} in TableGen descriptions. NFC.Toma Tabacu2015-05-081-3/+3
| | | | | | | | | | | | | | Summary: Instead of explicitly adding the IsFP64bit and NotFP64bit predicates through AdditionalRequires. Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D9566 llvm-svn: 236835
* [mips][microMIPS] Fix opcodes of MFHC1 and MTHC1 instructions.Jozef Kolek2014-11-191-4/+4
| | | | | | Differential Revision: http://reviews.llvm.org/D6169 llvm-svn: 222355
* [mips][mips64r6] bc1[tf] are not available on MIPS32r6/MIPS64r6Daniel Sanders2014-06-121-2/+2
| | | | | | | | | | | | | | | | | | | | Summary: Also tightened up the acceptable condition operand for these instructions on MIPS-I to MIPS-III. Support for $fcc[1-7] was added in MIPS-IV. Prior to that only $fcc0 is acceptable. We currently don't optimize (BEQZ (NOT $a), $target) and similar. It's probably best to do this in InstCombine. Depends on D4111 Reviewers: jkolek, zoran.jovanovic, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D4112 llvm-svn: 210787
* [mips][mips64r6] [sl][duw]xc1 are not available on MIPS32r6/MIPS64r6Daniel Sanders2014-06-121-4/+4
| | | | | | | | | | | | | | | | | Summary: Folded mips64-fp-indexed-ls.ll into fp-indexed-ls.ll. To do so, the zext's in mips64-fp-indexed-ls.ll were changed to implicit sign extensions (performed by getelementptr). This does not affect the purpose of the test. Depends on D4004 Reviewers: zoran.jovanovic, jkolek, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D4110 llvm-svn: 210784
* [mips] Marked up instructions added in MIPS32r2 and tested that IAS for ↵Daniel Sanders2014-05-131-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | -mcpu=mips(2|32) does not accept them Summary: This required a new instruction group representing the 32-bit subset of MIPS-3 that was available in MIPS32R2. To limit the number of tests required, only one 32-bit and one 64-bit ISA prior to MIPS32/MIPS64 are tested. rdhwr has been deliberately left without an ISA annotation for now. This is because the assembler and CodeGen disagree on when the instruction is available. Strictly speaking, it is only available in MIPS32r2 and MIPS64r2. However, it is emulated by a kernel trap on earlier ISA's and is necessary for TLS so CodeGen should emit it on older ISA's too. Depends on D3696 Reviewers: vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3697 llvm-svn: 208690
* [mips] Marked up instructions added in MIPS-V and tested that IAS for ↵Daniel Sanders2014-05-121-2/+2
| | | | | | | | | | | | | | | | | | | | | | -mcpu=mips[1234] does not accept them Summary: This required a new instruction group representing the 32-bit subset of MIPS-V that was available in MIPS32R2 Most of these instructions are correctly rejected but with the wrong error message. These have been placed in a separate test for now. It happens because many of the MIPS V instructions have not been implemented. Depends on D3694 Reviewers: vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3695 llvm-svn: 208546
* [mips] Split Instruction.Predicates into smaller lists and re-join them with ↵Daniel Sanders2014-05-071-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | !listconcat Summary: The overall idea is to chop the Predicates list into subsets that are usually overridden independently. This allows subclasses to partially override the predicates of their superclasses without having to re-add all the existing predicates. This patch starts the process by moving HasStdEnc into a new EncodingPredicates list and almost everything else into AdditionalPredicates. It has revealed a couple likely bugs where 'let Predicates' has removed the HasStdEnc predicate. No functional change (confirmed by diffing tablegen-erated files). Depends on D3549, D3506 Reviewers: vmedic Differential Revision: http://reviews.llvm.org/D3550 llvm-svn: 208184
* [mips] Move HasStdEnc to the front of the predicates lists.Daniel Sanders2014-05-071-1/+1
| | | | | | | | | | | | | | | | | | Summary: This will make it easier to prove that a more complicated change in the following commit is non-functional. No functional change. Depends on D3506 Reviewers: vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3549 llvm-svn: 208179
* [mips][sched] Split IIFmoveC1 into II_M[FT]C1, II_M[FT]HC1, II_DM[FT]C1Daniel Sanders2014-01-211-4/+4
| | | | | | No functional change since the InstrItinData's have been duplicated. llvm-svn: 199748
* [mips][sched] Split IIFStore into II_S[WD]C1, and II_S[WDU]XC1Daniel Sanders2014-01-211-4/+4
| | | | | | No functional change since the InstrItinData's have been duplicated. llvm-svn: 199747
* [mips][sched] Split IIFLoad into II_L[WD]C1, and II_L[WDU]XC1Daniel Sanders2014-01-211-4/+4
| | | | | | No functional change since the InstrItinData's have been duplicated. llvm-svn: 199743
* [mips][sched] Renamed II_FsqrtSingle and II_FsqrtDouble to II_SQRT_S and ↵Daniel Sanders2014-01-211-3/+3
| | | | | | | | II_SQRT_D respectively No functional change llvm-svn: 199741
* [mips][sched] Renamed II_FdivSingle and II_FdivDouble to II_DIV_S and ↵Daniel Sanders2014-01-211-2/+2
| | | | | | | | II_DIV_D respectively No functional change llvm-svn: 199738
* [mips][sched] Split IIFmulDouble into II_MUL_D, II_MADD_D, II_MSUB_D, ↵Daniel Sanders2014-01-211-7/+7
| | | | | | | | II_NMADD_D, and II_NMSUB_S No functional change since the InstrItinData's have been duplicated. llvm-svn: 199737
* [mips][sched] Split IIFmulSingle into II_MUL_S, II_MADD_S, II_MSUB_S, ↵Daniel Sanders2014-01-211-5/+5
| | | | | | | | II_NMADD_S, and II_NMSUB_S No functional change since the InstrItinData's have been duplicated. llvm-svn: 199734
* [mips][sched] Split IIFadd into II_ADD_[DS], II_SUB_[DS]Daniel Sanders2014-01-211-4/+4
| | | | | | No functional change since the InstrItinData's have been duplicated. llvm-svn: 199732
* [mips][sched] Split IIFcmp into II_C_CC_[SD]Daniel Sanders2014-01-211-2/+2
| | | | | | No functional change since the InstrItinData's have been duplicated. llvm-svn: 199728
* [mips][sched] Split IIFmove into II_C[FT]C1, II_MOV[FNTZ]_[SD], II_MOV_[SD]Daniel Sanders2014-01-211-20/+20
| | | | | | No functional change since the InstrItinData's have been duplicated. llvm-svn: 199727
* [mips][sched] Split IIFcvt into II_(ROUND|TRUNC|CEIL|FLOOR|CVT), II_ABS, II_NEGDaniel Sanders2014-01-211-20/+20
| | | | | | No functional change since the InstrItinData's have been duplicated. llvm-svn: 199722
* Support for microMIPS FPU instructions 2.Zoran Jovanovic2013-12-251-0/+49
| | | | llvm-svn: 198009
* Support for microMIPS FPU instructions 1.Zoran Jovanovic2013-12-201-0/+99
llvm-svn: 197815
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