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| author | Simon Dardis <simon.dardis@imgtec.com> | 2016-10-05 16:11:01 +0000 |
|---|---|---|
| committer | Simon Dardis <simon.dardis@imgtec.com> | 2016-10-05 16:11:01 +0000 |
| commit | f45a59f80b213c2a23d9b022b56c8f347a901fe5 (patch) | |
| tree | 9a3b9157f2a157b08522f797f3f7ff829fdd6b42 /llvm/lib/Target/Mips/MicroMipsInstrFPU.td | |
| parent | 447164dea22a9a56f1ea45511acc0a040551e767 (diff) | |
| download | bcm5719-llvm-f45a59f80b213c2a23d9b022b56c8f347a901fe5.tar.gz bcm5719-llvm-f45a59f80b213c2a23d9b022b56c8f347a901fe5.zip | |
Recommit: "[mips] Add rsqrt, recip for MIPS"
Add rsqrt.[ds], recip.[ds] for MIPS. Correct the microMIPS definitions for
architecture support and register usage.
Reviewers: vkalintiris, zoran.jovanoic
Differential Review: https://reviews.llvm.org/D24499
llvm-svn: 283334
Diffstat (limited to 'llvm/lib/Target/Mips/MicroMipsInstrFPU.td')
| -rw-r--r-- | llvm/lib/Target/Mips/MicroMipsInstrFPU.td | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/llvm/lib/Target/Mips/MicroMipsInstrFPU.td b/llvm/lib/Target/Mips/MicroMipsInstrFPU.td index ed92265e47f..fc83761e409 100644 --- a/llvm/lib/Target/Mips/MicroMipsInstrFPU.td +++ b/llvm/lib/Target/Mips/MicroMipsInstrFPU.td @@ -141,6 +141,16 @@ let AdditionalPredicates = [InMicroMips] in { MFC1_FM_MM<0x40>; def CTC1_MM : MMRel, MTC1_FT<"ctc1", CCROpnd, GPR32Opnd, II_CTC1>, MFC1_FM_MM<0x60>; + def RECIP_S_MM : MMRel, ABSS_FT<"recip.s", FGR32Opnd, FGR32Opnd, + II_RECIP_S>, + ROUND_W_FM_MM<0b0, 0b01001000>; + def RECIP_D_MM : MMRel, ABSS_FT<"recip.d", AFGR64Opnd, AFGR64Opnd, + II_RECIP_D>, ROUND_W_FM_MM<0b1, 0b01001000>; + def RSQRT_S_MM : MMRel, ABSS_FT<"rsqrt.s", FGR32Opnd, FGR32Opnd, + II_RECIP_S>, + ROUND_W_FM_MM<0b0, 0b00001000>; + def RSQRT_D_MM : MMRel, ABSS_FT<"rsqrt.d", AFGR64Opnd, AFGR64Opnd, + II_RECIP_D>, ROUND_W_FM_MM<0b1, 0b00001000>; } let DecoderNamespace = "MicroMips", DecoderMethod = "DecodeFMemMMR2" in { def LDC1_MM : MMRel, LW_FT<"ldc1", AFGR64Opnd, mem_mm_16, II_LDC1, load>, |
