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| author | Hrvoje Varga <Hrvoje.Varga@imgtec.com> | 2016-05-11 12:12:24 +0000 |
|---|---|---|
| committer | Hrvoje Varga <Hrvoje.Varga@imgtec.com> | 2016-05-11 12:12:24 +0000 |
| commit | 52c9bed858013b413dea5c96e4a40fdd4c62a198 (patch) | |
| tree | 093d5e1640f07083684514f4b36379369edba39b /llvm/lib/Target/Mips/MicroMipsInstrFPU.td | |
| parent | ea7f539a54658ceba3489051ef907390a51514f8 (diff) | |
| download | bcm5719-llvm-52c9bed858013b413dea5c96e4a40fdd4c62a198.tar.gz bcm5719-llvm-52c9bed858013b413dea5c96e4a40fdd4c62a198.zip | |
[mips][microMIPS] Implement CFC*, CTC* and LDC* instructions
Differential Revision: http://reviews.llvm.org/D19713
llvm-svn: 269176
Diffstat (limited to 'llvm/lib/Target/Mips/MicroMipsInstrFPU.td')
| -rw-r--r-- | llvm/lib/Target/Mips/MicroMipsInstrFPU.td | 7 |
1 files changed, 6 insertions, 1 deletions
diff --git a/llvm/lib/Target/Mips/MicroMipsInstrFPU.td b/llvm/lib/Target/Mips/MicroMipsInstrFPU.td index 3208f2b9f89..6357b8c5408 100644 --- a/llvm/lib/Target/Mips/MicroMipsInstrFPU.td +++ b/llvm/lib/Target/Mips/MicroMipsInstrFPU.td @@ -20,7 +20,6 @@ def FSUB_MM : MMRel, ADDS_FT<"sub.d", AFGR64Opnd, II_SUB_D, 0, fsub>, def LWC1_MM : MMRel, LW_FT<"lwc1", FGR32Opnd, II_LWC1, load>, LW_FM_MM<0x27>; def SWC1_MM : MMRel, SW_FT<"swc1", FGR32Opnd, II_SWC1, store>, LW_FM_MM<0x26>; -def LDC1_MM : MMRel, LW_FT<"ldc1", AFGR64Opnd, II_LDC1, load>, LW_FM_MM<0x2f>; def SDC1_MM : MMRel, SW_FT<"sdc1", AFGR64Opnd, II_SDC1, store>, LW_FM_MM<0x2e>; def LWXC1_MM : MMRel, LWXC1_FT<"lwxc1", FGR32Opnd, II_LWXC1, load>, @@ -147,4 +146,10 @@ let AdditionalPredicates = [InMicroMips] in { MFC1_FM_MM<0xe0>, ISA_MIPS32R2, FGR_32; def MFHC1_MM : MMRel, MFC1_FT<"mfhc1", GPR32Opnd, AFGR64Opnd, II_MFHC1>, MFC1_FM_MM<0xc0>, ISA_MIPS32R2, FGR_32; + def LDC1_MM : MMRel, LW_FT<"ldc1", AFGR64Opnd, II_LDC1, load>, + LW_FM_MM<0x2f>, FGR_32 { + let DecoderNamespace = "MicroMips"; + let DecoderMethod = "DecodeFMemMMR6"; + let BaseOpcode = "LDC132"; + } } |
