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| author | Daniel Sanders <daniel.sanders@imgtec.com> | 2014-01-21 14:50:20 +0000 |
|---|---|---|
| committer | Daniel Sanders <daniel.sanders@imgtec.com> | 2014-01-21 14:50:20 +0000 |
| commit | bf8aa22902e71b8d33b63548931544682e5855cc (patch) | |
| tree | bee18c6ca1030b30d745b4ef36e9a1320312547a /llvm/lib/Target/Mips/MicroMipsInstrFPU.td | |
| parent | 7706107e6f6e17dfa8e1f2d85c44cd7430c32e52 (diff) | |
| download | bcm5719-llvm-bf8aa22902e71b8d33b63548931544682e5855cc.tar.gz bcm5719-llvm-bf8aa22902e71b8d33b63548931544682e5855cc.zip | |
[mips][sched] Split IIFStore into II_S[WD]C1, and II_S[WDU]XC1
No functional change since the InstrItinData's have been duplicated.
llvm-svn: 199747
Diffstat (limited to 'llvm/lib/Target/Mips/MicroMipsInstrFPU.td')
| -rw-r--r-- | llvm/lib/Target/Mips/MicroMipsInstrFPU.td | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/llvm/lib/Target/Mips/MicroMipsInstrFPU.td b/llvm/lib/Target/Mips/MicroMipsInstrFPU.td index d2e9c2302b0..02b10499da0 100644 --- a/llvm/lib/Target/Mips/MicroMipsInstrFPU.td +++ b/llvm/lib/Target/Mips/MicroMipsInstrFPU.td @@ -18,18 +18,18 @@ def FSUB_MM : MMRel, ADDS_FT<"sub.d", AFGR64Opnd, II_SUB_D, 0, fsub>, ADDS_FM_MM<1, 0x70>; def LWC1_MM : MMRel, LW_FT<"lwc1", FGR32Opnd, II_LWC1, load>, LW_FM_MM<0x27>; -def SWC1_MM : MMRel, SW_FT<"swc1", FGR32Opnd, IIFStore, store>, +def SWC1_MM : MMRel, SW_FT<"swc1", FGR32Opnd, II_SWC1, store>, LW_FM_MM<0x26>; def LDC1_MM : MMRel, LW_FT<"ldc1", AFGR64Opnd, II_LDC1, load>, LW_FM_MM<0x2f>; -def SDC1_MM : MMRel, SW_FT<"sdc1", AFGR64Opnd, IIFStore, store>, +def SDC1_MM : MMRel, SW_FT<"sdc1", AFGR64Opnd, II_SDC1, store>, LW_FM_MM<0x2e>; def LWXC1_MM : MMRel, LWXC1_FT<"lwxc1", FGR32Opnd, II_LWXC1, load>, LWXC1_FM_MM<0x48>; -def SWXC1_MM : MMRel, SWXC1_FT<"swxc1", FGR32Opnd, IIFStore, store>, +def SWXC1_MM : MMRel, SWXC1_FT<"swxc1", FGR32Opnd, II_SWXC1, store>, SWXC1_FM_MM<0x88>; def LUXC1_MM : MMRel, LWXC1_FT<"luxc1", AFGR64Opnd, II_LUXC1>, LWXC1_FM_MM<0x148>; -def SUXC1_MM : MMRel, SWXC1_FT<"suxc1", AFGR64Opnd, IIFStore>, +def SUXC1_MM : MMRel, SWXC1_FT<"suxc1", AFGR64Opnd, II_SUXC1>, SWXC1_FM_MM<0x188>; def FCMP_S32_MM : MMRel, CEQS_FT<"s", FGR32, II_C_CC_S, MipsFPCmp>, |
