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| author | Daniel Sanders <daniel.sanders@imgtec.com> | 2014-05-13 11:45:36 +0000 |
|---|---|---|
| committer | Daniel Sanders <daniel.sanders@imgtec.com> | 2014-05-13 11:45:36 +0000 |
| commit | 387fc15d2ca055f934ef4f067408cf8bcbf43bf1 (patch) | |
| tree | 9e52fd980378e1be53082b6a7a453d655f95a33c /llvm/lib/Target/Mips/MicroMipsInstrFPU.td | |
| parent | ea3514ecdbfa154fa04c01eaa7a82166b7890e22 (diff) | |
| download | bcm5719-llvm-387fc15d2ca055f934ef4f067408cf8bcbf43bf1.tar.gz bcm5719-llvm-387fc15d2ca055f934ef4f067408cf8bcbf43bf1.zip | |
[mips] Marked up instructions added in MIPS32r2 and tested that IAS for -mcpu=mips(2|32) does not accept them
Summary:
This required a new instruction group representing the 32-bit subset of
MIPS-3 that was available in MIPS32R2.
To limit the number of tests required, only one 32-bit and one 64-bit ISA
prior to MIPS32/MIPS64 are tested.
rdhwr has been deliberately left without an ISA annotation for now. This is
because the assembler and CodeGen disagree on when the instruction is
available. Strictly speaking, it is only available in MIPS32r2 and
MIPS64r2. However, it is emulated by a kernel trap on earlier ISA's and is
necessary for TLS so CodeGen should emit it on older ISA's too.
Depends on D3696
Reviewers: vmedic
Reviewed By: vmedic
Differential Revision: http://reviews.llvm.org/D3697
llvm-svn: 208690
Diffstat (limited to 'llvm/lib/Target/Mips/MicroMipsInstrFPU.td')
| -rw-r--r-- | llvm/lib/Target/Mips/MicroMipsInstrFPU.td | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/llvm/lib/Target/Mips/MicroMipsInstrFPU.td b/llvm/lib/Target/Mips/MicroMipsInstrFPU.td index 7457ad86b2f..d95f9b07b95 100644 --- a/llvm/lib/Target/Mips/MicroMipsInstrFPU.td +++ b/llvm/lib/Target/Mips/MicroMipsInstrFPU.td @@ -70,9 +70,9 @@ def FSQRT_MM : MMRel, ABSS_FT<"sqrt.d", AFGR64Opnd, AFGR64Opnd, II_SQRT_D, fsqrt>, ROUND_W_FM_MM<1, 0x28>; def CVT_L_S_MM : MMRel, ABSS_FT<"cvt.l.s", FGR64Opnd, FGR32Opnd, II_CVT>, - ROUND_W_FM_MM<0, 0x4>; + ROUND_W_FM_MM<0, 0x4>, INSN_MIPS3_32R2; def CVT_L_D64_MM : MMRel, ABSS_FT<"cvt.l.d", FGR64Opnd, FGR64Opnd, II_CVT>, - ROUND_W_FM_MM<1, 0x4>; + ROUND_W_FM_MM<1, 0x4>, INSN_MIPS3_32R2; def FABS_S_MM : MMRel, ABSS_FT<"abs.s", FGR32Opnd, FGR32Opnd, II_ABS, fabs>, ABS_FM_MM<0, 0xd>; @@ -124,9 +124,9 @@ def MFC1_MM : MMRel, MFC1_FT<"mfc1", GPR32Opnd, FGR32Opnd, def MTC1_MM : MMRel, MTC1_FT<"mtc1", FGR32Opnd, GPR32Opnd, II_MTC1, bitconvert>, MFC1_FM_MM<0xa0>; def MFHC1_MM : MMRel, MFC1_FT<"mfhc1", GPR32Opnd, FGRH32Opnd, II_MFHC1>, - MFC1_FM_MM<3>; + MFC1_FM_MM<3>, ISA_MIPS32R2; def MTHC1_MM : MMRel, MTC1_FT<"mthc1", FGRH32Opnd, GPR32Opnd, II_MTHC1>, - MFC1_FM_MM<7>; + MFC1_FM_MM<7>, ISA_MIPS32R2; def MADD_S_MM : MMRel, MADDS_FT<"madd.s", FGR32Opnd, II_MADD_S, fadd>, MADDS_FM_MM<0x1>; |
