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| author | Toma Tabacu <toma.tabacu@imgtec.com> | 2015-05-08 12:15:04 +0000 |
|---|---|---|
| committer | Toma Tabacu <toma.tabacu@imgtec.com> | 2015-05-08 12:15:04 +0000 |
| commit | 8b3345ba7c37183ebf177c77e14d9585028c35ff (patch) | |
| tree | aa25b364bc4ee2a0efddfcb186f6a9a1d38c0246 /llvm/lib/Target/Mips/MicroMipsInstrFPU.td | |
| parent | 3e6f5155313f0d463d743b214c28a369581b3b46 (diff) | |
| download | bcm5719-llvm-8b3345ba7c37183ebf177c77e14d9585028c35ff.tar.gz bcm5719-llvm-8b3345ba7c37183ebf177c77e14d9585028c35ff.zip | |
[mips] Only use FGR_{32,64} in TableGen descriptions. NFC.
Summary: Instead of explicitly adding the IsFP64bit and NotFP64bit predicates through AdditionalRequires.
Reviewers: dsanders
Reviewed By: dsanders
Subscribers: llvm-commits
Differential Revision: http://reviews.llvm.org/D9566
llvm-svn: 236835
Diffstat (limited to 'llvm/lib/Target/Mips/MicroMipsInstrFPU.td')
| -rw-r--r-- | llvm/lib/Target/Mips/MicroMipsInstrFPU.td | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/llvm/lib/Target/Mips/MicroMipsInstrFPU.td b/llvm/lib/Target/Mips/MicroMipsInstrFPU.td index fae70598fa3..004b0d51f4b 100644 --- a/llvm/lib/Target/Mips/MicroMipsInstrFPU.td +++ b/llvm/lib/Target/Mips/MicroMipsInstrFPU.td @@ -95,7 +95,7 @@ def FNEG_MM : MMRel, ABSS_FT<"neg.d", AFGR64Opnd, AFGR64Opnd, II_NEG, fneg>, ABS_FM_MM<1, 0x2d>; def FMOV_D32_MM : MMRel, ABSS_FT<"mov.d", AFGR64Opnd, AFGR64Opnd, II_MOV_D>, - ABS_FM_MM<1, 0x1>, AdditionalRequires<[NotFP64bit]>; + ABS_FM_MM<1, 0x1>, FGR_32; def MOVZ_I_S_MM : MMRel, CMov_I_F_FT<"movz.s", GPR32Opnd, FGR32Opnd, II_MOVZ_S>, CMov_I_F_FM_MM<0x78, 0>; @@ -124,9 +124,9 @@ def MFC1_MM : MMRel, MFC1_FT<"mfc1", GPR32Opnd, FGR32Opnd, def MTC1_MM : MMRel, MTC1_FT<"mtc1", FGR32Opnd, GPR32Opnd, II_MTC1, bitconvert>, MFC1_FM_MM<0xa0>; def MFHC1_MM : MMRel, MFC1_FT<"mfhc1", GPR32Opnd, AFGR64Opnd, II_MFHC1>, - MFC1_FM_MM<0xc0>, ISA_MIPS32R2, AdditionalRequires<[NotFP64bit]>; + MFC1_FM_MM<0xc0>, ISA_MIPS32R2, FGR_32; def MTHC1_MM : MMRel, MTC1_64_FT<"mthc1", AFGR64Opnd, GPR32Opnd, II_MTHC1>, - MFC1_FM_MM<0xe0>, ISA_MIPS32R2, AdditionalRequires<[NotFP64bit]>; + MFC1_FM_MM<0xe0>, ISA_MIPS32R2, FGR_32; def MADD_S_MM : MMRel, MADDS_FT<"madd.s", FGR32Opnd, II_MADD_S, fadd>, MADDS_FM_MM<0x1>; |
