| Commit message (Expand) | Author | Age | Files | Lines |
|---|
| * | Use MCRegister in copyPhysReg | Matt Arsenault | 2019-11-11 | 1 | -2/+2 |
| * | Finish moving TargetRegisterInfo::isVirtualRegister() and friends to llvm::Re... | Daniel Sanders | 2019-08-01 | 1 | -9/+8 |
| * | Update the file headers across all of the LLVM projects in the monorepo | Chandler Carruth | 2019-01-19 | 1 | -4/+3 |
| * | [ARM] Allow the scheduler to clone a node with glue to avoid a copy CPSR ↔ ... | Roger Ferrer Ibanez | 2018-01-31 | 1 | -0/+13 |
| * | [ARM] Accept a subset of Thumb GPR register class when emitting an SP-relative | Momchil Velikov | 2018-01-26 | 1 | -2/+2 |
| * | Remove redundant includes from lib/Target/ARM. | Michael Zolotukhin | 2017-12-13 | 1 | -1/+0 |
| * | Sort the remaining #include lines in include/... and lib/.... | Chandler Carruth | 2017-06-06 | 1 | -1/+1 |
| * | Re-commit r301040 "X86: Don't emit zero-byte functions on Windows" | Hans Wennborg | 2017-04-21 | 1 | -2/+2 |
| * | Revert r301040 "X86: Don't emit zero-byte functions on Windows" | Hans Wennborg | 2017-04-21 | 1 | -2/+2 |
| * | X86: Don't emit zero-byte functions on Windows | Hans Wennborg | 2017-04-21 | 1 | -2/+2 |
| * | In Thumb1, materialize a move between low registers as a `movs`, if CPSR isn'... | Artyom Skrobov | 2017-03-07 | 1 | -5/+11 |
| * | [ARM] CodeGen: Remove AddDefaultPred. NFC. | Diana Picus | 2017-01-13 | 1 | -11/+20 |
| * | MachineFunction: Return reference for getFrameInfo(); NFC | Matthias Braun | 2016-07-28 | 1 | -2/+2 |
| * | Don't pass Reloc::Model to places that already have it. NFC. | Rafael Espindola | 2016-06-28 | 1 | -6/+7 |
| * | Pass DebugLoc and SDLoc by const ref. | Benjamin Kramer | 2016-06-12 | 1 | -3/+3 |
| * | PseudoSourceValue: Replace global manager with a manager in a machine function. | Alex Lorenz | 2015-08-11 | 1 | -10/+6 |
| * | Rename all references to old mailing lists to new lists.llvm.org address. | Tanya Lattner | 2015-08-05 | 1 | -1/+1 |
| * | MC: Modernize MCOperand API naming. NFC. | Jim Grosbach | 2015-05-13 | 1 | -4/+4 |
| * | Remove the need to cache the subtarget in the ARM TargetRegisterInfo | Eric Christopher | 2015-03-12 | 1 | -2/+1 |
| * | Get the cached subtarget off the MachineFunction rather than | Eric Christopher | 2015-02-20 | 1 | -1/+1 |
| * | Lower thumbv4t & thumbv5 lo->lo copies through a push-pop sequence | Jonathan Roelofs | 2014-08-20 | 1 | -2/+23 |
| * | [ARM] In dynamic-no-pic mode, ARM's post-RA pseudo expansion was incorrectly | Akira Hatanaka | 2014-08-02 | 1 | -3/+3 |
| * | [stack protector] Fix a potential security bug in stack protector where the | Akira Hatanaka | 2014-07-25 | 1 | -0/+9 |
| * | Prune includes in ARM target. | Craig Topper | 2014-03-22 | 1 | -1/+0 |
| * | Don't cache the instruction and register info from the TargetMachine, because | Bill Wendling | 2013-06-07 | 1 | -1/+1 |
| * | Use the new script to sort the includes of every file under lib. | Chandler Carruth | 2012-12-03 | 1 | -1/+1 |
| * | Convert more uses of XXXRegisterClass to &XXXRegClass. No functional change s... | Craig Topper | 2012-04-20 | 1 | -4/+4 |
| * | Prune some includes | Craig Topper | 2012-03-27 | 1 | -1/+0 |
| * | Reorder includes to match coding standards. Fix an issue or two exposed by that. | Craig Topper | 2012-03-17 | 1 | -1/+0 |
| * | ARM implement TargetInstrInfo::getNoopForMachoTarget() | Jim Grosbach | 2012-02-28 | 1 | -1/+10 |
| * | Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, MSP430,... | Jia Liu | 2012-02-18 | 1 | -1/+1 |
| * | Make use of MachinePointerInfo::getFixedStack. This removes all mention | Jay Foad | 2011-11-15 | 1 | -5/+2 |
| * | Refact ARM Thumb1 tMOVr instruction family. | Jim Grosbach | 2011-06-30 | 1 | -11/+1 |
| * | Thumb1 register to register MOV instruction is predicable. | Jim Grosbach | 2011-06-30 | 1 | -2/+2 |
| * | Refactor away tSpill and tRestore pseudos in ARM backend. | Jim Grosbach | 2011-06-29 | 1 | -2/+2 |
| * | Merge XXXGenRegisterNames.inc into XXXGenRegisterInfo.inc | Evan Cheng | 2011-06-28 | 1 | -1/+0 |
| * | Move callee-saved regs spills / reloads to TFI | Anton Korobeynikov | 2010-11-27 | 1 | -74/+0 |
| * | convert targets to the new MF.getMachineMemOperand interface. | Chris Lattner | 2010-09-21 | 1 | -4/+6 |
| * | RISC architectures get their memory operand folding for free. | Jakob Stoklund Olesen | 2010-07-11 | 1 | -76/+0 |
| * | Replace copyRegToReg with copyPhysReg for ARM. | Jakob Stoklund Olesen | 2010-07-11 | 1 | -24/+17 |
| * | Thumb1 functions using @llvm.returnaddress were not saving the incoming LR. | Bob Wilson | 2010-06-22 | 1 | -3/+3 |
| * | Next round of tail call changes. Register used in a tail | Dale Johannesen | 2010-06-15 | 1 | -3/+3 |
| * | Implement @llvm.returnaddress. rdar://8015977. | Evan Cheng | 2010-05-22 | 1 | -5/+21 |
| * | Add a DebugLoc argument to TargetInstrInfo::copyRegToReg, so that it | Dan Gohman | 2010-05-06 | 1 | -4/+2 |
| * | Add argument TargetRegisterInfo to loadRegFromStackSlot and storeRegToStackSlot. | Evan Cheng | 2010-05-06 | 1 | -8/+10 |
| * | use DebugLoc default ctor instead of DebugLoc::getUnknownLoc() | Chris Lattner | 2010-04-02 | 1 | -4/+4 |
| * | Don't leak a MachineInstruction from Thumb1InstrInfo::restoreCalleeSavedRegis... | Jeffrey Yasskin | 2010-03-22 | 1 | -0/+2 |
| * | Change ARM ld/st multiple instructions to have variant instructions for | Bob Wilson | 2010-03-13 | 1 | -2/+0 |
| * | Update Thumb1 storeRegToStackSlot() and loadRegFromStackSlot() to properly | Jim Grosbach | 2010-01-15 | 1 | -2/+6 |
| * | Silence a clang warning about the deprecated (but perfectly reasonable in | John McCall | 2009-12-16 | 1 | -2/+2 |
