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* ARM fix encoding of VMOV.f32 and VMOV.f64 immediates.Jim Grosbach2011-09-301-27/+0
| | | | | | | | | | | Encode the immediate into its 8-bit form as part of isel rather than later, which simplifies things for mapping the encoding bits, allows the removal of the custom disassembler decoding hook, makes the operand printer trivial, and prepares things more cleanly for handling these in the asm parser. rdar://10211428 llvm-svn: 140834
* ASR #32 is not allowed on Thumb2 USAT and SSAT instructions.Owen Anderson2011-09-261-0/+14
| | | | llvm-svn: 140560
* Reapply r140412 (Thumb2 reg-reg loads cannot target SP or PC), with invalid ↵Owen Anderson2011-09-231-1/+1
| | | | | | testcases updated. llvm-svn: 140415
* Revert r140412. This affects more instructions than intended.Owen Anderson2011-09-231-1/+1
| | | | llvm-svn: 140413
* Thumb2 register-shifted-register loads cannot target the PC or the SP.Owen Anderson2011-09-231-1/+1
| | | | llvm-svn: 140412
* tMOVSr is not allowed in an IT block either.Owen Anderson2011-09-191-0/+1
| | | | llvm-svn: 140104
* CPS instructions are UNPREDICTABLE inside IT blocks.Owen Anderson2011-09-191-0/+4
| | | | llvm-svn: 140102
* Thumb2 TBB and TBH instructions are only allowed at the end of IT blocks, ↵Owen Anderson2011-09-191-0/+2
| | | | | | not in the middle. llvm-svn: 140079
* Thumb2 assembly parsing and encoding for TBB/TBH.Jim Grosbach2011-09-191-0/+18
| | | | llvm-svn: 140078
* Handle STRT (and friends) like LDRT (and friends) for decoding purposes. ↵Owen Anderson2011-09-191-0/+3
| | | | | | Port over additional encoding tests to decoding tests. llvm-svn: 140032
* Bitfield mask instructions are unpredictable if the encoded LSB is higher ↵Owen Anderson2011-09-161-1/+4
| | | | | | than the encoded MSB. llvm-svn: 139972
* Fix bitfield decoding based on Eli's feedback.Owen Anderson2011-09-161-4/+3
| | | | llvm-svn: 139969
* Thumb2 pre-indexed loads/stores use the restricted GPR set for Rt.Owen Anderson2011-09-161-1/+1
| | | | llvm-svn: 139965
* Fix disassembly of Thumb2 BFI instructions with bit range of [0, 32).Owen Anderson2011-09-161-0/+4
| | | | llvm-svn: 139964
* Fix disassembly of Thumb2 LDRSH with a #-0 offset.Owen Anderson2011-09-161-1/+4
| | | | llvm-svn: 139943
* Don't attach annotations to MCInst's. Instead, have the disassembler ↵Owen Anderson2011-09-151-4/+8
| | | | | | return, and the printer accept, an annotation string which can be passed through if the client cares about annotations. llvm-svn: 139876
* Nested IT blocks are UNPREDICTABLE. Mark them as such when disassembling them.Owen Anderson2011-09-141-0/+4
| | | | llvm-svn: 139736
* Port more encoding tests to decoding tests, and correct an improper Thumb2 ↵Owen Anderson2011-09-121-0/+32
| | | | | | pre-indexed load decoding this uncovered. llvm-svn: 139522
* LDM writeback is not allowed if Rn is in the target register list.Owen Anderson2011-09-091-0/+19
| | | | llvm-svn: 139432
* Fix assembly/disassembly of Thumb2 ADR instructions with immediate operands.Owen Anderson2011-09-091-0/+18
| | | | llvm-svn: 139422
* Thumb unconditional branches are allowed in IT blocks, and therefore should ↵Owen Anderson2011-09-091-4/+14
| | | | | | have a predicate operand, unlike conditional branches. llvm-svn: 139415
* Thumb2 assembly parsing and encoding for LDREX/LDREXB/LDREXD/LDREXH.Jim Grosbach2011-09-091-0/+17
| | | | llvm-svn: 139381
* All conditional branches are disallowed in IT blocks, not just CBZ/CBNZ.Owen Anderson2011-09-081-2/+3
| | | | llvm-svn: 139329
* Soft fail CBZ/CBNZ in the disassembler if they appear inside an IT block.Owen Anderson2011-09-081-12/+21
| | | | llvm-svn: 139328
* Thumb2 assembly parsing and encoding for LDRD(immediate).Jim Grosbach2011-09-081-0/+76
| | | | | | Refactor operand handling for STRD as well. Tests for that forthcoming. llvm-svn: 139322
* Remove the "common" set of instructions shared between ARM and Thumb2 modes. ↵Owen Anderson2011-09-081-18/+0
| | | | | | This is no longer needed now that Thumb2 has its own copy of the STC/LDC instructions. llvm-svn: 139268
* Create Thumb2 versions of STC/LDC, and reenable the relevant tests.Owen Anderson2011-09-071-0/+28
| | | | llvm-svn: 139256
* Second of a three-patch series aiming to fix MSR/MRS on Cortex-M. This adds ↵James Molloy2011-09-071-16/+23
| | | | | | predicate checking to the Disassembler. llvm-svn: 139250
* Port more assembler tests over to disassembler tests, and fix a minor logic ↵Owen Anderson2011-09-071-1/+1
| | | | | | error that exposed. llvm-svn: 139240
* Refactor instprinter and mcdisassembler to take a SubtargetInfo. Add -mattr= ↵James Molloy2011-09-071-8/+9
| | | | | | handling to llvm-mc. Reviewed by Owen Anderson. llvm-svn: 139237
* Merge the ARM disassembler header into the implementation file, since it is ↵Owen Anderson2011-09-012-85/+54
| | | | | | not externally exposed. llvm-svn: 138982
* Fix 80 columns violations.Owen Anderson2011-09-011-449/+655
| | | | llvm-svn: 138980
* Fix up r137380 based on post-commit review by Jim Grosbach.James Molloy2011-09-011-593/+595
| | | | llvm-svn: 138948
* The asm parser currently selects the wrong encoding for non-conditional ↵Owen Anderson2011-08-311-4/+4
| | | | | | Thumb2 branches. However, this exposed a number of situations where the decoder was too permissive in allowing invalid instructions to decode successful. Specify additional fixed bits to close those gaps. llvm-svn: 138910
* Fix issues with disassembly of IT instructions involving condition codes ↵Owen Anderson2011-08-301-28/+30
| | | | | | other the EQ/NE. Discovered by roundtrip testing. llvm-svn: 138840
* Improve encoding support for BLX with immediat eoperands, and fix a BLX ↵Owen Anderson2011-08-261-9/+0
| | | | | | decoding bug this uncovered. llvm-svn: 138675
* Spelling fail.Owen Anderson2011-08-261-1/+1
| | | | llvm-svn: 138667
* invalid-LDR_PRE-arm.txt was already passing, but for the wrong reasons. We ↵Owen Anderson2011-08-261-2/+49
| | | | | | were failing to specify enough fixed bits of LDR_PRE/LDRB_PRE, resulting in decoding conflicts. Separate them into immediate vs. register versions, allowing us to specify the necessary fixed bits. This in turn results in the test being decoded properly, and being rejected as UNPREDICTABLE rather than a hard failure. llvm-svn: 138653
* Update for feedback from Jim.Owen Anderson2011-08-261-3/+3
| | | | llvm-svn: 138642
* ARMDisassembler: Always return a size, even when disassembling fails.Benjamin Kramer2011-08-261-3/+11
| | | | | | This should fix PR10772. llvm-svn: 138636
* Support an extension of ARM asm syntax to allow immediate operands to ADR ↵Owen Anderson2011-08-261-6/+9
| | | | | | instructions. This is helpful for disassembler testing, and indeed exposed a disassembler bug that is also fixed here. llvm-svn: 138635
* Fix PR10755 by checking for invalid predicate codes from UNPREDICTABLE t2IT ↵Owen Anderson2011-08-261-0/+2
| | | | | | | | instructions when decoding their successors. This is the last disassembly crash detected by exhaustive Thumb2 instruction space. Major thanks to Chandler Carruth for making this kind of exhaustive testing possible. llvm-svn: 138625
* Port over additional encoding tests to decoding tests, and fix an operand ↵Owen Anderson2011-08-251-1/+1
| | | | | | ordering bug this exposed. llvm-svn: 138575
* Perform more thorough checking of t2IT mask parameters, which fixes all ↵Owen Anderson2011-08-241-0/+13
| | | | | | remaining crashers when disassembling the entire 16-bit instruction space. llvm-svn: 138507
* Be careful not to walk off the end of the operand info list while updating ↵Owen Anderson2011-08-241-1/+2
| | | | | | VFP predicates. llvm-svn: 138492
* Move TargetRegistry and TargetSelect from Target to Support where they belong.Evan Cheng2011-08-241-1/+1
| | | | | | These are strictly utilities for registering targets and components. llvm-svn: 138450
* Be stricter in enforcing IT instruction predicate values, so that we don't ↵Owen Anderson2011-08-241-0/+14
| | | | | | end up trying to print out an illegal predicate. llvm-svn: 138443
* Fix decoding of Thumb2 prefetch instructions, which account for all the ↵Owen Anderson2011-08-231-3/+9
| | | | | | remaining Thumb2 decoding failures found by randomized testing so far. llvm-svn: 138341
* Fix Thumb2 decoding of CPS instructions to mirror ARM decoding of the same ↵Owen Anderson2011-08-231-9/+43
| | | | | | instructions. llvm-svn: 138339
* Reject invalid imod values in t2CPS instructions.Owen Anderson2011-08-221-1/+10
| | | | llvm-svn: 138306
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