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| author | Owen Anderson <resistor@mac.com> | 2011-08-23 17:45:18 +0000 |
|---|---|---|
| committer | Owen Anderson <resistor@mac.com> | 2011-08-23 17:45:18 +0000 |
| commit | 9b7bd15d0b865a1fddb3e32254dcd4ef4068b145 (patch) | |
| tree | b9fb49305b1be0c0fb3b4e653768171e9b87edbf /llvm/lib/Target/ARM/Disassembler | |
| parent | e364ad540a740bf86b6c3172a19c93830e912bdc (diff) | |
| download | bcm5719-llvm-9b7bd15d0b865a1fddb3e32254dcd4ef4068b145.tar.gz bcm5719-llvm-9b7bd15d0b865a1fddb3e32254dcd4ef4068b145.zip | |
Fix Thumb2 decoding of CPS instructions to mirror ARM decoding of the same instructions.
llvm-svn: 138339
Diffstat (limited to 'llvm/lib/Target/ARM/Disassembler')
| -rw-r--r-- | llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp | 52 |
1 files changed, 43 insertions, 9 deletions
diff --git a/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp b/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp index cc2a583ab87..5711b69796e 100644 --- a/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp +++ b/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp @@ -103,6 +103,8 @@ static DecodeStatus DecodeSMLAInstruction(llvm::MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder); static DecodeStatus DecodeCPSInstruction(llvm::MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder); +static DecodeStatus DecodeT2CPSInstruction(llvm::MCInst &Inst, unsigned Insn, + uint64_t Address, const void *Decoder); static DecodeStatus DecodeAddrModeImm12Operand(llvm::MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder); static DecodeStatus DecodeAddrMode5Operand(llvm::MCInst &Inst, unsigned Val, @@ -179,8 +181,6 @@ static DecodeStatus DecodeVMOVSRR(llvm::MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder); static DecodeStatus DecodeVMOVRRS(llvm::MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder); -static DecodeStatus DecodeCPSIMod(llvm::MCInst &Inst, unsigned Insn, - uint64_t Address, const void *Decoder); static DecodeStatus DecodeThumbAddSpecialReg(llvm::MCInst &Inst, uint16_t Insn, uint64_t Address, const void *Decoder); @@ -1393,6 +1393,47 @@ static DecodeStatus DecodeCPSInstruction(llvm::MCInst &Inst, unsigned Insn, return S; } +static DecodeStatus DecodeT2CPSInstruction(llvm::MCInst &Inst, unsigned Insn, + uint64_t Address, const void *Decoder) { + unsigned imod = fieldFromInstruction32(Insn, 9, 2); + unsigned M = fieldFromInstruction32(Insn, 8, 1); + unsigned iflags = fieldFromInstruction32(Insn, 5, 3); + unsigned mode = fieldFromInstruction32(Insn, 0, 5); + + DecodeStatus S = Success; + + // imod == '01' --> UNPREDICTABLE + // NOTE: Even though this is technically UNPREDICTABLE, we choose to + // return failure here. The '01' imod value is unprintable, so there's + // nothing useful we could do even if we returned UNPREDICTABLE. + + if (imod == 1) CHECK(S, Fail); + + if (imod && M) { + Inst.setOpcode(ARM::t2CPS3p); + Inst.addOperand(MCOperand::CreateImm(imod)); + Inst.addOperand(MCOperand::CreateImm(iflags)); + Inst.addOperand(MCOperand::CreateImm(mode)); + } else if (imod && !M) { + Inst.setOpcode(ARM::t2CPS2p); + Inst.addOperand(MCOperand::CreateImm(imod)); + Inst.addOperand(MCOperand::CreateImm(iflags)); + if (mode) CHECK(S, Unpredictable); + } else if (!imod && M) { + Inst.setOpcode(ARM::t2CPS1p); + Inst.addOperand(MCOperand::CreateImm(mode)); + if (iflags) CHECK(S, Unpredictable); + } else { + // imod == '00' && M == '0' --> UNPREDICTABLE + Inst.setOpcode(ARM::t2CPS1p); + Inst.addOperand(MCOperand::CreateImm(mode)); + CHECK(S, Unpredictable); + } + + return S; +} + + static DecodeStatus DecodeSMLAInstruction(llvm::MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) { DecodeStatus S = Success; @@ -3242,10 +3283,3 @@ static DecodeStatus DecodeVMOVRRS(llvm::MCInst &Inst, unsigned Insn, return S; } -static DecodeStatus DecodeCPSIMod(llvm::MCInst &Inst, unsigned Val, - uint64_t Address, const void *Decoder) { - if (Val == 0x1) return Fail; - Inst.addOperand(MCOperand::CreateImm(Val)); - return Success; -} - |
