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| author | Owen Anderson <resistor@mac.com> | 2011-08-26 21:47:57 +0000 |
|---|---|---|
| committer | Owen Anderson <resistor@mac.com> | 2011-08-26 21:47:57 +0000 |
| commit | 240d20af79cdfe9abd51425c18bbbb06ec072c62 (patch) | |
| tree | 973e86b9ab0e33a6a710c88985b2de68a21fa458 /llvm/lib/Target/ARM/Disassembler | |
| parent | f0be551d68267d52b9ca7e852754da6a683eb7c1 (diff) | |
| download | bcm5719-llvm-240d20af79cdfe9abd51425c18bbbb06ec072c62.tar.gz bcm5719-llvm-240d20af79cdfe9abd51425c18bbbb06ec072c62.zip | |
Spelling fail.
llvm-svn: 138667
Diffstat (limited to 'llvm/lib/Target/ARM/Disassembler')
| -rw-r--r-- | llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp b/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp index 3cdcb050596..6b87dfd0df7 100644 --- a/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp +++ b/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp @@ -2324,7 +2324,7 @@ static DecodeStatus DecodeThumbAddSpecialReg(llvm::MCInst &Inst, uint16_t Insn, default: return Fail; case ARM::tADR: - break; // tADR does not explicitly represent the PC as an oeprand. + break; // tADR does not explicitly represent the PC as an operand. case ARM::tADDrSPi: Inst.addOperand(MCOperand::CreateReg(ARM::SP)); break; |
