Support an extension of ARM asm syntax to allow immediate operands to ADR instructions. This is helpful for disassembler testing, and indeed exposed a disassembler bug that is also fixed here.

llvm-svn: 138635

1 files changed, 9 insertions, 6 deletions

diff --git a/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp b/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
index f1c5ce8bc52..3fd06a998be 100644
--- a/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
+++ b/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
@@ -2310,12 +2310,15 @@ static DecodeStatus DecodeThumbAddSpecialReg(llvm::MCInst &Inst, uint16_t Insn,
 
   CHECK(S, DecodetGPRRegisterClass(Inst, dst, Address, Decoder));
 
-  if (Inst.getOpcode() == ARM::tADR)
-    Inst.addOperand(MCOperand::CreateReg(ARM::PC));
-  else if (Inst.getOpcode() == ARM::tADDrSPi)
-    Inst.addOperand(MCOperand::CreateReg(ARM::SP));
-  else
-    return Fail;
+  switch(Inst.getOpcode()) {
+    case ARM::tADR:
+      break;
+    case ARM::tADDrSPi:
+      Inst.addOperand(MCOperand::CreateReg(ARM::SP));
+      break;
+    default:
+      return Fail;
+  }
 
   Inst.addOperand(MCOperand::CreateImm(imm));
   return S;