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| author | Owen Anderson <resistor@mac.com> | 2011-09-07 21:10:42 +0000 |
|---|---|---|
| committer | Owen Anderson <resistor@mac.com> | 2011-09-07 21:10:42 +0000 |
| commit | 18d17aa6b74c3078f2021d8efcabf7a6bd910b9c (patch) | |
| tree | 6ec31d3bef3794b1a11008e440dce156403c9249 /llvm/lib/Target/ARM/Disassembler | |
| parent | fed3ab5bc115d02c84070a57293e820188ebb765 (diff) | |
| download | bcm5719-llvm-18d17aa6b74c3078f2021d8efcabf7a6bd910b9c.tar.gz bcm5719-llvm-18d17aa6b74c3078f2021d8efcabf7a6bd910b9c.zip | |
Create Thumb2 versions of STC/LDC, and reenable the relevant tests.
llvm-svn: 139256
Diffstat (limited to 'llvm/lib/Target/ARM/Disassembler')
| -rw-r--r-- | llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp | 28 |
1 files changed, 28 insertions, 0 deletions
diff --git a/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp b/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp index fa9eed4b47b..13e410c139e 100644 --- a/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp +++ b/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp @@ -997,6 +997,22 @@ static DecodeStatus DecodeCopMemInstruction(llvm::MCInst &Inst, unsigned Insn, case ARM::STCL_PRE: case ARM::STCL_POST: case ARM::STCL_OPTION: + case ARM::t2LDC_OFFSET: + case ARM::t2LDC_PRE: + case ARM::t2LDC_POST: + case ARM::t2LDC_OPTION: + case ARM::t2LDCL_OFFSET: + case ARM::t2LDCL_PRE: + case ARM::t2LDCL_POST: + case ARM::t2LDCL_OPTION: + case ARM::t2STC_OFFSET: + case ARM::t2STC_PRE: + case ARM::t2STC_POST: + case ARM::t2STC_OPTION: + case ARM::t2STCL_OFFSET: + case ARM::t2STCL_PRE: + case ARM::t2STCL_POST: + case ARM::t2STCL_OPTION: if (coproc == 0xA || coproc == 0xB) return MCDisassembler::Fail; break; @@ -1021,6 +1037,12 @@ static DecodeStatus DecodeCopMemInstruction(llvm::MCInst &Inst, unsigned Insn, case ARM::STCL_POST: case ARM::LDC2L_POST: case ARM::STC2L_POST: + case ARM::t2LDC_OPTION: + case ARM::t2LDCL_OPTION: + case ARM::t2STC_OPTION: + case ARM::t2STCL_OPTION: + case ARM::t2LDCL_POST: + case ARM::t2STCL_POST: break; default: Inst.addOperand(MCOperand::CreateReg(0)); @@ -1040,6 +1062,8 @@ static DecodeStatus DecodeCopMemInstruction(llvm::MCInst &Inst, unsigned Insn, switch (Inst.getOpcode()) { case ARM::LDCL_POST: case ARM::STCL_POST: + case ARM::t2LDCL_POST: + case ARM::t2STCL_POST: case ARM::LDC2L_POST: case ARM::STC2L_POST: imm |= U << 8; @@ -1051,6 +1075,10 @@ static DecodeStatus DecodeCopMemInstruction(llvm::MCInst &Inst, unsigned Insn, case ARM::STCL_OPTION: case ARM::STC2_OPTION: case ARM::STC2L_OPTION: + case ARM::t2LDC_OPTION: + case ARM::t2LDCL_OPTION: + case ARM::t2STC_OPTION: + case ARM::t2STCL_OPTION: Inst.addOperand(MCOperand::CreateImm(imm)); break; default: |
