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| author | Owen Anderson <resistor@mac.com> | 2011-08-25 18:30:18 +0000 |
|---|---|---|
| committer | Owen Anderson <resistor@mac.com> | 2011-08-25 18:30:18 +0000 |
| commit | 5e30972cfff2a49cb0d5952a74cc10c10b996112 (patch) | |
| tree | 5d7d6c296f993e9a51082dbdd61500d214d8400f /llvm/lib/Target/ARM/Disassembler | |
| parent | 69e9464340af6889c163bd867c2b5b8812b7985a (diff) | |
| download | bcm5719-llvm-5e30972cfff2a49cb0d5952a74cc10c10b996112.tar.gz bcm5719-llvm-5e30972cfff2a49cb0d5952a74cc10c10b996112.zip | |
Port over additional encoding tests to decoding tests, and fix an operand ordering bug this exposed.
llvm-svn: 138575
Diffstat (limited to 'llvm/lib/Target/ARM/Disassembler')
| -rw-r--r-- | llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp b/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp index 83a8f800608..0d945fdf591 100644 --- a/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp +++ b/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp @@ -2539,8 +2539,8 @@ static DecodeStatus DecodeThumbAddSPReg(llvm::MCInst &Inst, uint16_t Insn, Rdm |= fieldFromInstruction16(Insn, 7, 1) << 3; CHECK(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder)); - Inst.addOperand(MCOperand::CreateReg(ARM::SP)); CHECK(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder)); + Inst.addOperand(MCOperand::CreateReg(ARM::SP)); } else if (Inst.getOpcode() == ARM::tADDspr) { unsigned Rm = fieldFromInstruction16(Insn, 3, 4); |
