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path: root/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
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* ARM scheduling fix: compute predicated implicit use properly.Andrew Trick2012-06-221-3/+1
* Continue factoring computeOperandLatency. Use it for ARM hasHighOperandLatency.Andrew Trick2012-06-071-1/+2
* ARM getOperandLatency rewrite.Andrew Trick2012-06-071-85/+112
* ARM getOperandLatency should return -1 for unknown, consistent with APIAndrew Trick2012-06-071-1/+4
* Fix ARM getInstrLatency logic to work with the current API.Andrew Trick2012-06-071-13/+19
* misched: API for minimum vs. expected latency.Andrew Trick2012-06-051-8/+11
* Mark a static table as const. Shrink opcode size in static tables to uint16_t...Craig Topper2012-05-241-14/+9
* Fix use of uninitialized variable.David Blaikie2012-05-141-1/+1
* Add space before an open parenthesis in control flow statements.Manman Ren2012-05-111-2/+2
* ARM: peephole optimization to remove cmp instructionManman Ren2012-05-111-27/+119
* Revert: 156550 "ARM: peephole optimization to remove cmp instruction"Manman Ren2012-05-101-118/+27
* ARM: peephole optimization to remove cmp instructionManman Ren2012-05-101-27/+118
* Implement ARMBaseInstrInfo::commuteInstruction() for MOVCCr.Jakob Stoklund Olesen2012-04-041-0/+23
* Handle register copies for the new ARM register classes.Jakob Stoklund Olesen2012-03-291-19/+41
* Spill DPair registers, not just QPR.Jakob Stoklund Olesen2012-03-281-2/+2
* ARM has a peephole optimization which looks for a def / use pair. The defEvan Cheng2012-03-261-0/+19
* Prune includes and replace uses of ARMRegisterInfo.h with ARMBaeRegisterInfo.hCraig Topper2012-03-261-1/+1
* ARM refactor more NEON VLD/VST instructions to use composite physregsJim Grosbach2012-03-061-18/+18
* Add <imp-def> operands when reloading into physregs.Jakob Stoklund Olesen2012-03-061-0/+4
* ARM refactor away a bunch of VLD/VST pseudo instructions.Jim Grosbach2012-03-051-25/+25
* Use <def,undef> operands when spilling NEON bundles.Jakob Stoklund Olesen2012-03-041-14/+12
* ARM implement TargetInstrInfo::getNoopForMachoTarget()Jim Grosbach2012-02-281-0/+4
* Clarify ARM calling conventions.Jakob Stoklund Olesen2012-02-221-0/+2
* Calls don't really change the stack pointer.Jakob Stoklund Olesen2012-02-211-1/+2
* Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, MSP430,...Jia Liu2012-02-181-1/+1
* Handle regmask operands in ARMInstrInfo.Jakob Stoklund Olesen2012-02-171-6/+8
* Fix ARMBaseInstrInfo::getInstrLatency for calls.Jakob Stoklund Olesen2012-02-171-1/+1
* Convert assert(0) to llvm_unreachableCraig Topper2012-02-071-3/+1
* DefinesPredicate should only look for def operands. Patch by Ludwig Meier.Evan Cheng2012-02-051-1/+1
* More dead code removal (using -Wunreachable-code)David Blaikie2012-01-201-85/+81
* Reapply r146997, "Heed spill slot alignment on ARM."Jakob Stoklund Olesen2012-01-051-2/+3
* Revert r146997, "Heed spill slot alignment on ARM."Jakob Stoklund Olesen2012-01-031-3/+2
* ARM NEON assmebly parsing for VLD2 to all lanes instructions.Jim Grosbach2011-12-211-6/+12
* Heed spill slot alignment on ARM.Jakob Stoklund Olesen2011-12-201-2/+3
* Model ARM predicated write as read-mod-write. e.g.Evan Cheng2011-12-141-14/+41
* - Add MachineInstrBundle.h and MachineInstrBundle.cpp. This includes a functionEvan Cheng2011-12-141-8/+129
* ARM assembly parsing and encoding for VLD2 with writeback.Jim Grosbach2011-12-091-12/+24
* Add bundle aware API for querying instruction properties and switch the codeEvan Cheng2011-12-071-12/+11
* Revert r145971: "Use conservative size estimate for tBR_JTr."Jakob Stoklund Olesen2011-12-061-3/+3
* First chunk of MachineInstr bundle support.Evan Cheng2011-12-061-2/+1
* Use conservative size estimate for tBR_JTr.Jakob Stoklund Olesen2011-12-061-3/+3
* ARM parsing for VLD1 all lanes, with writeback.Jim Grosbach2011-11-301-6/+12
* Enable -widen-vmovs by default.Jakob Stoklund Olesen2011-11-151-1/+1
* Make use of MachinePointerInfo::getFixedStack. This removes all mentionJay Foad2011-11-151-4/+2
* ARM assembly parsing and encoding for VLD1 with writeback.Jim Grosbach2011-10-251-1/+2
* Nuke dead code. Nothing generates the VLD1d64QPseudo_UPD instruction.Jim Grosbach2011-10-241-1/+0
* ARM assembly parsing and encoding for VLD1 w/ writeback.Jim Grosbach2011-10-241-2/+2
* ARM refactor am6offset usage for VLD1.Jim Grosbach2011-10-241-8/+16
* Use ARM/t2PseudoInst class from ARM/Thumb2 special adds/subs patterns.Andrew Trick2011-10-181-1/+0
* Fix -widen-vmovs liveness issues.Jakob Stoklund Olesen2011-10-121-3/+29
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