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| author | Jim Grosbach <grosbach@apple.com> | 2011-10-25 00:14:01 +0000 |
|---|---|---|
| committer | Jim Grosbach <grosbach@apple.com> | 2011-10-25 00:14:01 +0000 |
| commit | 17ec1a19e5b28c45ae1280b5bedb2fc884312d70 (patch) | |
| tree | 4d5c6981b0ca2ad839764ba66cae1f903f63bfa8 /llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp | |
| parent | 93127aecb961cbfad3e3c2fc7929ac9d55536b34 (diff) | |
| download | bcm5719-llvm-17ec1a19e5b28c45ae1280b5bedb2fc884312d70.tar.gz bcm5719-llvm-17ec1a19e5b28c45ae1280b5bedb2fc884312d70.zip | |
ARM assembly parsing and encoding for VLD1 with writeback.
Four entry register lists.
llvm-svn: 142882
Diffstat (limited to 'llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp')
| -rw-r--r-- | llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp b/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp index 23fae3e0806..7a7267a719b 100644 --- a/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp +++ b/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp @@ -2440,7 +2440,8 @@ ARMBaseInstrInfo::getOperandLatency(const InstrItineraryData *ItinData, case ARM::VLD4d8_UPD: case ARM::VLD4d16_UPD: case ARM::VLD4d32_UPD: - case ARM::VLD1d64Q_UPD: + case ARM::VLD1d64Qwb_fixed: + case ARM::VLD1d64Qwb_register: case ARM::VLD4q8_UPD: case ARM::VLD4q16_UPD: case ARM::VLD4q32_UPD: |
