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| author | Jim Grosbach <grosbach@apple.com> | 2012-03-06 22:01:44 +0000 |
|---|---|---|
| committer | Jim Grosbach <grosbach@apple.com> | 2012-03-06 22:01:44 +0000 |
| commit | 13a292cc74422c16f6eee1cddad9e523318eb0d3 (patch) | |
| tree | e0eda22948e3bab241dfcf4bdf353730b326cd48 /llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp | |
| parent | 75383bf34dc8069f260e8639783c481224b90dc6 (diff) | |
| download | bcm5719-llvm-13a292cc74422c16f6eee1cddad9e523318eb0d3.tar.gz bcm5719-llvm-13a292cc74422c16f6eee1cddad9e523318eb0d3.zip | |
ARM refactor more NEON VLD/VST instructions to use composite physregs
Register pair VLD1/VLD2 all-lanes instructions. Kill off more of the
pseudos as a result.
llvm-svn: 152150
Diffstat (limited to 'llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp')
| -rw-r--r-- | llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp | 36 |
1 files changed, 18 insertions, 18 deletions
diff --git a/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp b/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp index 7a9de93268c..366e2fa4552 100644 --- a/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp +++ b/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp @@ -2760,24 +2760,24 @@ ARMBaseInstrInfo::getOperandLatency(const InstrItineraryData *ItinData, case ARM::VLD4q8oddPseudo_UPD: case ARM::VLD4q16oddPseudo_UPD: case ARM::VLD4q32oddPseudo_UPD: - case ARM::VLD1DUPq8Pseudo: - case ARM::VLD1DUPq16Pseudo: - case ARM::VLD1DUPq32Pseudo: - case ARM::VLD1DUPq8PseudoWB_fixed: - case ARM::VLD1DUPq16PseudoWB_fixed: - case ARM::VLD1DUPq32PseudoWB_fixed: - case ARM::VLD1DUPq8PseudoWB_register: - case ARM::VLD1DUPq16PseudoWB_register: - case ARM::VLD1DUPq32PseudoWB_register: - case ARM::VLD2DUPd8Pseudo: - case ARM::VLD2DUPd16Pseudo: - case ARM::VLD2DUPd32Pseudo: - case ARM::VLD2DUPd8PseudoWB_fixed: - case ARM::VLD2DUPd16PseudoWB_fixed: - case ARM::VLD2DUPd32PseudoWB_fixed: - case ARM::VLD2DUPd8PseudoWB_register: - case ARM::VLD2DUPd16PseudoWB_register: - case ARM::VLD2DUPd32PseudoWB_register: + case ARM::VLD1DUPq8: + case ARM::VLD1DUPq16: + case ARM::VLD1DUPq32: + case ARM::VLD1DUPq8wb_fixed: + case ARM::VLD1DUPq16wb_fixed: + case ARM::VLD1DUPq32wb_fixed: + case ARM::VLD1DUPq8wb_register: + case ARM::VLD1DUPq16wb_register: + case ARM::VLD1DUPq32wb_register: + case ARM::VLD2DUPd8: + case ARM::VLD2DUPd16: + case ARM::VLD2DUPd32: + case ARM::VLD2DUPd8wb_fixed: + case ARM::VLD2DUPd16wb_fixed: + case ARM::VLD2DUPd32wb_fixed: + case ARM::VLD2DUPd8wb_register: + case ARM::VLD2DUPd16wb_register: + case ARM::VLD2DUPd32wb_register: case ARM::VLD4DUPd8Pseudo: case ARM::VLD4DUPd16Pseudo: case ARM::VLD4DUPd32Pseudo: |
