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path: root/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
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* Radar numbers don't belong in source code.Evan Cheng2013-02-211-2/+0
* Move all of the header files which are involved in modelling the LLVM IRChandler Carruth2013-01-021-3/+3
* Remove the Function::getFnAttributes method in favor of using the AttributeSetBill Wendling2012-12-301-2/+3
* MachineInstrBuilderize ARM.Jakob Stoklund Olesen2012-12-201-3/+4
* Remove the explicit MachineInstrBuilder(MI) constructor.Jakob Stoklund Olesen2012-12-191-3/+4
* Rename the 'Attributes' class to 'Attribute'. It's going to represent a singl...Bill Wendling2012-12-191-1/+1
* Use the new script to sort the includes of every file under lib.Chandler Carruth2012-12-031-4/+4
* Remove all references to TargetInstrInfoImpl.Jakob Stoklund Olesen2012-11-281-5/+5
* misched: Target-independent support for load/store clustering.Andrew Trick2012-11-121-0/+6
* Add GPRPair Register class to ARM.Jakob Stoklund Olesen2012-10-261-0/+19
* misched: Use the TargetSchedModel interface wherever possible.Andrew Trick2012-10-101-12/+0
* whitespaceAndrew Trick2012-10-101-3/+3
* Create enums for the different attributes.Bill Wendling2012-10-091-1/+2
* Add LLVM support for Swift.Bob Wilson2012-09-291-9/+458
* Remove the `hasFnAttr' method from Function.Bill Wendling2012-09-261-1/+1
* More domain conversion; convert VFP VMOVS to NEON instructions in more cases ...James Molloy2012-09-181-13/+56
* Implement getNumLDMAddresses and expose through ARMBaseInstrInfo.Andrew Trick2012-09-141-0/+31
* This patch introduces A15 as a target in LLVM.Silviu Baranga2012-09-131-13/+13
* Don't attempt to use flags from predicated instructions.Jakob Stoklund Olesen2012-09-101-2/+8
* Use predication instead of pseudo-opcodes when folding into MOVCC.Jakob Stoklund Olesen2012-09-051-56/+31
* Strip old MachineInstrs *after* we know we can put them back.Tim Northover2012-09-051-6/+6
* Limit domain conversion to cases where it won't break dep chains.Tim Northover2012-09-011-12/+48
* Add support for moving pure S-register to NEON pipeline if desiredTim Northover2012-08-301-2/+71
* Refactor setExecutionDomain to be clearer about what it's doing and more robust.Tim Northover2012-08-291-45/+53
* Cleanup sloppy code. Jakob's review.Andrew Trick2012-08-291-4/+3
* Fix ARM vector copies of overlapping register tuples.Andrew Trick2012-08-291-0/+13
* cleanupAndrew Trick2012-08-291-21/+19
* Revert r162713: "Add ATOMIC_LDR* pseudo-instructions to model atomic_load on ...Jakob Stoklund Olesen2012-08-281-10/+10
* Add ATOMIC_LDR* pseudo-instructions to model atomic_load on ARM.Jakob Stoklund Olesen2012-08-271-10/+10
* Make sure we add the predicate after all of the registers are added.Bill Wendling2012-08-271-2/+3
* Add a missing def flag.Jakob Stoklund Olesen2012-08-211-4/+2
* Avoid folding ADD instructions with FI operands.Jakob Stoklund Olesen2012-08-171-0/+3
* Implement NEON domain switching for scalar <-> S-register vmovs on ARMTim Northover2012-08-171-15/+97
* Add ADD and SUB to the predicable ARM instructions.Jakob Stoklund Olesen2012-08-161-0/+20
* Handle ARM MOVCC optimization in PeepholeOptimizer.Jakob Stoklund Olesen2012-08-161-3/+64
* Fold predicable instructions into MOVCC / t2MOVCC.Jakob Stoklund Olesen2012-08-151-0/+49
* Recognize vst1.64 / vld1.64 with 3 and 4 regs as load from / store to stack s...Anton Korobeynikov2012-08-041-0/+4
* Add stack spill / reload instructions for DTriple and DQuad register classes,...Anton Korobeynikov2012-08-041-3/+43
* Fix a typo (the the => the)Sylvestre Ledru2012-07-231-1/+1
* ARM: fix typo in commentsManman Ren2012-07-111-1/+1
* ARM: Fix optimizeCompare to correctly check safe condition.Manman Ren2012-07-111-9/+14
* Revert accidental checkin.Andrew Trick2012-07-021-3/+2
* Reapply "Make NumMicroOps a variable in the subtarget's instruction itinerary."Andrew Trick2012-07-021-10/+11
* ARM: Clean up optimizeCompare in peephole, no functional change.Manman Ren2012-06-291-80/+73
* Add SrcReg2 to analyzeCompare and optimizeCompareInstr to handle CompareManman Ren2012-06-291-14/+21
* Revert "Make NumMicroOps a variable in the subtarget's instruction itinerary."Andrew Trick2012-06-291-9/+9
* Make NumMicroOps a variable in the subtarget's instruction itinerary.Andrew Trick2012-06-291-9/+9
* Add a missing check to avoid dereference null. No sensible test case possible...Evan Cheng2012-06-261-0/+2
* ARM: update peephole optimization.Manman Ren2012-06-251-2/+18
* ARM scheduling fix: don't guess at implicit operand latency.Andrew Trick2012-06-221-5/+9
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