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| author | Manman Ren <mren@apple.com> | 2012-06-25 21:49:38 +0000 |
|---|---|---|
| committer | Manman Ren <mren@apple.com> | 2012-06-25 21:49:38 +0000 |
| commit | 606953fbe76744eca6bc8c0c9e35ddcddaa1da29 (patch) | |
| tree | 03a8974dcc5d0a731bf5d62369c78b754e447570 /llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp | |
| parent | e1db0daf251438a7392c32e4ca821fde074c2fd0 (diff) | |
| download | bcm5719-llvm-606953fbe76744eca6bc8c0c9e35ddcddaa1da29.tar.gz bcm5719-llvm-606953fbe76744eca6bc8c0c9e35ddcddaa1da29.zip | |
ARM: update peephole optimization.
More condition codes are included when deciding whether to remove cmp after
a sub instruction. Specifically, we extend from GE|LT|GT|LE to
GE|LT|GT|LE|HS|LS|HI|LO|EQ|NE. If we have "sub a, b; cmp b, a; movhs", we
should be able to replace with "sub a, b; movls".
rdar: 11725965
llvm-svn: 159166
Diffstat (limited to 'llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp')
| -rw-r--r-- | llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp | 20 |
1 files changed, 18 insertions, 2 deletions
diff --git a/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp b/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp index e30f6d200ca..58f4e160de8 100644 --- a/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp +++ b/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp @@ -1875,7 +1875,9 @@ OptimizeCompareInstr(MachineInstr *CmpInstr, unsigned SrcReg, int CmpMask, } // Check whether the current instruction is SUB(r1, r2) or SUB(r2, r1). - if (SrcReg2 != 0 && Instr.getOpcode() == ARM::SUBrr && + if (SrcReg2 != 0 && + (Instr.getOpcode() == ARM::SUBrr || + Instr.getOpcode() == ARM::t2SUBrr) && ((Instr.getOperand(1).getReg() == SrcReg && Instr.getOperand(2).getReg() == SrcReg2) || (Instr.getOperand(1).getReg() == SrcReg2 && @@ -1976,6 +1978,12 @@ OptimizeCompareInstr(MachineInstr *CmpInstr, unsigned SrcReg, int CmpMask, case ARMCC::LT: case ARMCC::GT: case ARMCC::LE: + case ARMCC::HS: + case ARMCC::LS: + case ARMCC::HI: + case ARMCC::LO: + case ARMCC::EQ: + case ARMCC::NE: // If we have SUB(r1, r2) and CMP(r2, r1), the condition code based // on CMP needs to be updated to be based on SUB. // Push the condition code operands to OperandsToUpdate. @@ -2023,7 +2031,15 @@ OptimizeCompareInstr(MachineInstr *CmpInstr, unsigned SrcReg, int CmpMask, case ARMCC::GE: NewCC = ARMCC::LE; break; case ARMCC::LT: NewCC = ARMCC::GT; break; case ARMCC::GT: NewCC = ARMCC::LT; break; - case ARMCC::LE: NewCC = ARMCC::GT; break; + case ARMCC::LE: NewCC = ARMCC::GE; break; + case ARMCC::HS: NewCC = ARMCC::LS; break; + case ARMCC::LS: NewCC = ARMCC::HS; break; + case ARMCC::HI: NewCC = ARMCC::LO; break; + case ARMCC::LO: NewCC = ARMCC::HI; break; + case ARMCC::EQ: + case ARMCC::NE: + NewCC = CC; + break; } OperandsToUpdate[i]->setImm(NewCC); } |
