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path: root/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
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* [C++] Use 'nullptr'. Target edition.Craig Topper2014-04-251-30/+31
* [cleanup] Lift using directives, DEBUG_TYPE definitions, and even someChandler Carruth2014-04-221-3/+3
* [Modules] Make Support/Debug.h modular. This requires it to not changeChandler Carruth2014-04-211-0/+2
* Spell the specialization namespace correctly.Benjamin Kramer2014-04-121-1/+3
* Make helper static and place random global into the llvm namespace.Benjamin Kramer2014-04-121-1/+1
* ARM: teach LLVM that Cortex-A7 is very similar to A8.Tim Northover2014-04-011-7/+8
* Fix PR19136: [ARM] Fix Folding SP Update into vpush/vpopWeiming Zhao2014-03-201-3/+13
* Phase 2 of the great MachineRegisterInfo cleanup. This time, we're changingOwen Anderson2014-03-131-2/+3
* Replace PROLOG_LABEL with a new CFI_INSTRUCTION.Rafael Espindola2014-03-071-1/+1
* Simplify. No functionality change.Rafael Espindola2014-03-071-10/+2
* [C++11] Replace llvm::next and llvm::prior with std::next and std::prev.Benjamin Kramer2014-03-021-4/+3
* ARMv8 IfConversion must skip narrow instructions that a) define CPSR and b) w...Artyom Skrobov2014-02-261-0/+14
* Test commitOliver Stannard2014-01-291-0/+1
* For ARM, fix assertuib failures for some ld/st 3/4 instruction with wirteback.Jiangning Liu2014-01-161-0/+2
* ARM AnalyzeBranch should ignore DEBUG_VALUES while analyzing terminators.Lang Hames2013-12-201-1/+1
* Bug 18149: [AArch32] VSel instructions has no ARMCC fieldWeiming Zhao2013-12-061-7/+34
* ARM: decide whether to use movw/movt based on "minsize" attribute.Tim Northover2013-12-021-3/+3
* ARM: add pseudo-instructions for lit-pool global materialisationTim Northover2013-12-021-1/+7
* ARM: fix bug in -Oz stack adjustment foldingTim Northover2013-12-011-7/+18
* ARM: remove special cases for Darwin dynamic-no-pic mode.Tim Northover2013-11-251-5/+1
* Fix a typo where we were creating <def,kill> operands instead ofLang Hames2013-11-221-1/+2
* [weak vtables] Remove a bunch of weak vtablesJuergen Ributzka2013-11-191-1/+1
* Revert r194865 and r194874.Alexey Samsonov2013-11-181-1/+1
* [weak vtables] Remove a bunch of weak vtablesJuergen Ributzka2013-11-151-1/+1
* Enable generating legacy IT block for AArch32Weiming Zhao2013-11-131-1/+1
* ARM: fold prologue/epilogue sp updates into push/pop for code sizeTim Northover2013-11-081-0/+97
* ARM: remove unnecessary state-tracking during frame lowering.Tim Northover2013-11-041-0/+8
* ARM: Thumb2 copy for GPRPair needs to use thumb instructions.Jim Grosbach2013-10-221-1/+1
* ARM: Clean up copyPhysReg() a bit.Jim Grosbach2013-10-221-27/+47
* ARM: optimizeSelect has to consider the previous register classMatthias Braun2013-10-041-4/+9
* [ARM] Warn on deprecated IT blocks in v8 AArch32 assembly.Amara Emerson2013-10-031-69/+2
* IfConverter: Use TargetSchedule for instruction latenciesArnold Schwaighofer2013-09-301-0/+18
* Fix spelling.Robert Wilhelm2013-09-141-1/+1
* [ARMv8] Prevent generation of deprecated IT blocks on ARMv8 in Thumb mode.Joey Gouly2013-09-091-4/+78
* Let t2LDRBi8 and t2LDRBi12 have same Base PointerRenato Golin2013-08-141-1/+14
* Refactor AnalyzeBranch on ARM. The previous version did not always analyzeLang Hames2013-07-191-88/+67
* Related to r181161 - Indirect branches may not be the last branch in a basicLang Hames2013-07-161-0/+7
* Fix ARM paired GPR COPY loweringJF Bastien2013-07-121-0/+3
* DebugInfo: remove target-specific Frame Index handling for DBG_VALUE MachineI...David Blaikie2013-06-161-10/+0
* Machine Model: Add MicroOpBufferSize and resource BufferSize.Andrew Trick2013-06-151-2/+1
* Don't cache the instruction and register info from the TargetMachine, becauseBill Wendling2013-06-071-2/+1
* ARMInstrInfo: Improve isSwiftFastImmShiftArnold Schwaighofer2013-06-051-0/+2
* Revert series of sched model patches until I figure out what is going on.Arnold Schwaighofer2013-06-041-2/+0
* ARMInstrInfo: Improve isSwiftFastImmShiftArnold Schwaighofer2013-06-041-0/+2
* ARM AnalyzeBranch should conservatively return true when it sees a predicatedEvan Cheng2013-05-051-3/+9
* ARM: Use ldrd/strd to spill 64-bit pairs when available.Tim Northover2013-04-211-17/+38
* ARM: don't add FrameIndex offset for LDMIA (has no immediate)Tim Northover2013-04-201-1/+1
* ARM scheduler model: Swift has varying latencies, uops for simple ALU opsArnold Schwaighofer2013-04-051-0/+12
* Enabling the generation of dependency breakers for partial updates on Cortex-...Silviu Baranga2013-03-271-7/+5
* Adding an A15 specific optimization pass for interactions between S/D/Q regis...Silviu Baranga2013-03-151-1/+1
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