diff options
| author | Anton Korobeynikov <asl@math.spbu.ru> | 2012-08-04 13:22:14 +0000 |
|---|---|---|
| committer | Anton Korobeynikov <asl@math.spbu.ru> | 2012-08-04 13:22:14 +0000 |
| commit | 3a4fdfeceb13ca3e8cf607323b53eaf71070c06a (patch) | |
| tree | 099178cd11bbd4ced3b7a757b36fba51bf670f15 /llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp | |
| parent | 218aaf6d04d9aaee77181d4f92b37cd7dbfe053e (diff) | |
| download | bcm5719-llvm-3a4fdfeceb13ca3e8cf607323b53eaf71070c06a.tar.gz bcm5719-llvm-3a4fdfeceb13ca3e8cf607323b53eaf71070c06a.zip | |
Recognize vst1.64 / vld1.64 with 3 and 4 regs as load from / store to stack stuff
(this corresponds by spilling/reloading regs in DTriple / DQuad reg classes).
No testcase, found by inspection.
llvm-svn: 161300
Diffstat (limited to 'llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp')
| -rw-r--r-- | llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp b/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp index 134aca8c0c6..057fd718fdb 100644 --- a/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp +++ b/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp @@ -888,6 +888,8 @@ ARMBaseInstrInfo::isStoreToStackSlot(const MachineInstr *MI, } break; case ARM::VST1q64: + case ARM::VST1d64TPseudo: + case ARM::VST1d64QPseudo: if (MI->getOperand(0).isFI() && MI->getOperand(2).getSubReg() == 0) { FrameIndex = MI->getOperand(0).getIndex(); @@ -1056,6 +1058,8 @@ ARMBaseInstrInfo::isLoadFromStackSlot(const MachineInstr *MI, } break; case ARM::VLD1q64: + case ARM::VLD1d64TPseudo: + case ARM::VLD1d64QPseudo: if (MI->getOperand(1).isFI() && MI->getOperand(0).getSubReg() == 0) { FrameIndex = MI->getOperand(1).getIndex(); |
