summaryrefslogtreecommitdiffstats
path: root/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
Commit message (Expand)AuthorAgeFilesLines
...
* AMDGPU: Try to fix (non-clang?) bot buildsMatt Arsenault2016-11-071-10/+10
* AMDGPU: Refactor copyPhysRegMatt Arsenault2016-11-071-0/+103
* AMDGPU: Stop creating unused virtual registersMatt Arsenault2016-11-011-2/+5
* AMDGPU: Fix using incorrect private resource with no allocationMatt Arsenault2016-10-281-1/+12
* Reapply "AMDGPU: Don't use offen if it is 0"Matt Arsenault2016-10-261-9/+95
* AMDGPU: Fix use-after-freesNicolai Haehnle2016-10-141-1/+1
* AMDGPU: Do not re-use tmpreg in spill/restore loweringMatthias Braun2016-10-051-2/+2
* AMDGPU: Factor SGPR spilling into separate functionsMatt Arsenault2016-10-041-129/+160
* AMDGPU: Fix typoMatt Arsenault2016-10-031-1/+1
* Revert "AMDGPU: Don't use offen if it is 0"Mehdi Amini2016-10-011-95/+9
* AMDGPU: Don't use offen if it is 0Matt Arsenault2016-10-011-9/+95
* AMDGPU: Rename spill operands to match real instructionMatt Arsenault2016-09-171-10/+10
* AMDGPU/SI: Add support for triples with the mesa3d operating systemTom Stellard2016-09-161-1/+2
* AMDGPU: Remove code I think is deadMatt Arsenault2016-09-131-27/+3
* AMDGPU: Implement is{LoadFrom|StoreTo}FrameIndexMatt Arsenault2016-09-101-2/+2
* AMDGPU] Assembler: better support for immediate literals in assembler.Sam Kolton2016-09-091-2/+4
* [AMDGPU] Wave and register controlsKonstantin Zhuravlyov2016-09-061-123/+178
* AMDGPU: Fix spilling of m0Matt Arsenault2016-09-031-2/+26
* AMDGPU/SI: Implement a custom MachineSchedStrategyTom Stellard2016-08-291-0/+6
* XXXTom Stellard2016-08-261-1/+1
* AMDGPU/SI: Use a better method for determining the largest pressure setsTom Stellard2016-08-261-9/+28
* AMDGPU: Remove custom getSubRegMatt Arsenault2016-08-111-72/+10
* MachineFunction: Return reference for getFrameInfo(); NFCMatthias Braun2016-07-281-10/+10
* AMDGPU/SI: Don't use reserved VGPRs for SGPR spillingTom Stellard2016-07-281-3/+6
* AMDGPU: Add HSA dispatch id intrinsicMatt Arsenault2016-07-221-1/+2
* AMDGPU/SI: Emit the number of SGPR and VGPR spillsMarek Olsak2016-07-131-0/+2
* AMDGPU: Enable trackLivenessAfterRegAllocMatt Arsenault2016-07-111-0/+5
* AMDGPU: fix local stack slot allocation bugsNicolai Haehnle2016-07-111-2/+8
* CodeGen: Use MachineInstr& in TargetInstrInfo, NFCDuncan P. N. Exon Smith2016-06-301-1/+1
* AMDGPU: Cleanup subtarget handling.Matt Arsenault2016-06-241-26/+22
* AMDGPU/SI: Propagate the Kill flag in storeRegToStackSlot and eliminateFrameI...Changpeng Fang2016-06-161-12/+26
* AMDGPU: Remove incorrect assertionMatt Arsenault2016-06-091-4/+0
* [AMDGPU][NFC] Rename ReserveTrapVGPRs -> ReserveRegsKonstantin Zhuravlyov2016-05-241-3/+3
* AMDGPU: Fix verifier error when spilling undef subregMatt Arsenault2016-05-181-3/+11
* AMDGPU/SI: Use v_readfirstlane_b32 when restoring SGPRs spilled to scratchTom Stellard2016-05-021-2/+1
* AMDGPU/SI: Set the kill flag on temp VGPRs used to restore SGPRs from scratchTom Stellard2016-05-021-1/+1
* AMDGPU/SI: Enable the post-ra schedulerTom Stellard2016-04-301-16/+11
* [AMDGPU] Move reserved vgpr count for trap handler usage to SIMachineFunction...Konstantin Zhuravlyov2016-04-261-2/+3
* [AMDGPU] Reserve VGPRs for trap handler usage if instructedKonstantin Zhuravlyov2016-04-261-0/+11
* AMDGPU: Add queue ptr intrinsicMatt Arsenault2016-04-251-1/+2
* Silence some "initialized but unused" warnings from MSVC -- the function bein...Aaron Ballman2016-04-181-13/+2
* AMDGPU: Enable LocalStackSlotAllocation passMatt Arsenault2016-04-161-0/+138
* AMDGPU: allow specifying a workgroup size that needs to fit in a compute unitTom Stellard2016-04-141-52/+73
* AMDGPU/SI: Add support for spilling VGPRs without having to scavenge registersTom Stellard2016-04-131-10/+27
* [AMDGPU][llvm-mc] Support of Trap Handler registers (TTMP0..11 and TBA/TMA)gi...Artem Tamazov2016-04-131-1/+25
* AMDGPU/SI: Add MachineBasicBlock parameter to SIInstrInfo::insertWaitStatesTom Stellard2016-04-071-2/+2
* AMDGPU: Cache information about register pressure setsTom Stellard2016-03-231-24/+33
* AMDGPU/SI: add llvm.amdgcn.buffer.load/store.format intrinsicsNicolai Haehnle2016-03-101-3/+3
* AMDGPU/SI: Add support for spiling SGPRs to scratch bufferTom Stellard2016-03-041-17/+69
* AMDGPU/SI: Enable frame index scavenging during PrologEpilogueInserterTom Stellard2016-03-041-7/+13
OpenPOWER on IntegriCloud