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| author | Tom Stellard <thomas.stellard@amd.com> | 2016-09-16 21:34:26 +0000 |
|---|---|---|
| committer | Tom Stellard <thomas.stellard@amd.com> | 2016-09-16 21:34:26 +0000 |
| commit | 0b76fc4c772c03beb6d09eef7e48ffc77a214c82 (patch) | |
| tree | 5a1fa69ae335f5977f104fa2699aa2ff17ba079f /llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp | |
| parent | aab6d5c52a2ffd9ed392d13ffcd23bd8156fd026 (diff) | |
| download | bcm5719-llvm-0b76fc4c772c03beb6d09eef7e48ffc77a214c82.tar.gz bcm5719-llvm-0b76fc4c772c03beb6d09eef7e48ffc77a214c82.zip | |
AMDGPU/SI: Add support for triples with the mesa3d operating system
Summary:
mesa3d will use the same kernel calling convention as amdhsa, but it will
handle everything else like the default 'unknown' OS type.
Reviewers: arsenm
Subscribers: arsenm, llvm-commits, kzhuravl
Differential Revision: https://reviews.llvm.org/D22783
llvm-svn: 281779
Diffstat (limited to 'llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp')
| -rw-r--r-- | llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp b/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp index 6804c0f6bb7..bcee76f5299 100644 --- a/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp +++ b/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp @@ -801,7 +801,8 @@ unsigned SIRegisterInfo::getPreloadedValue(const MachineFunction &MF, case SIRegisterInfo::PRIVATE_SEGMENT_WAVE_BYTE_OFFSET: return MFI->PrivateSegmentWaveByteOffsetSystemSGPR; case SIRegisterInfo::PRIVATE_SEGMENT_BUFFER: - assert(ST.isAmdHsaOS() && "Non-HSA ABI currently uses relocations"); + assert(ST.isAmdCodeObjectV2() && + "Non-CodeObjectV2 ABI currently uses relocations"); assert(MFI->hasPrivateSegmentBuffer()); return MFI->PrivateSegmentBufferUserSGPR; case SIRegisterInfo::KERNARG_SEGMENT_PTR: |
