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path: root/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
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* AMDGPU/SI: Detect uniform branches and emit s_cbranch instructionsTom Stellard2016-02-121-1/+4
* AMDGPU: Set flat_scratch from flat_scratch_init regMatt Arsenault2016-02-121-0/+5
* AMDGPU/SI: Make sure MIMG descriptors and samplers stay in SGPRsTom Stellard2016-02-111-0/+18
* AMDGPU: Release the scavenged offset register during VGPR spillNicolai Haehnle2016-02-101-1/+8
* AMDGPU/SI: Add SI Machine SchedulerNicolai Haehnle2016-01-131-1/+14
* AMDGPU/SI: Fold operands with sub-registersNicolai Haehnle2016-01-071-4/+30
* AMDGPU/SI: xnack_mask is always reserved on VINicolai Haehnle2016-01-071-31/+16
* AMDGPU: add +xnack featureNicolai Haehnle2016-01-041-6/+27
* AMDGPU: Avoid assertions after SGPR spilling failedNicolai Haehnle2016-01-041-10/+0
* AMDGPU: Fix off-by-one in SIRegisterInfo::eliminateFrameIndexNicolai Haehnle2015-12-171-6/+7
* Squelch unused variable warning in SIRegisterInfo.cpp.Matt Arsenault2015-12-011-1/+2
* AMDGPU: Rework how private buffer passed for HSAMatt Arsenault2015-11-301-18/+62
* AMDGPU: Rename enums to be consistent with HSA code object terminologyMatt Arsenault2015-11-301-14/+14
* AMDGPU: Remove SIPrepareScratchRegsMatt Arsenault2015-11-301-0/+19
* AMDGPU: Add llvm.amdgcn.dispatch.ptr intrinsicTom Stellard2015-11-261-0/+6
* Revert "Remove unnecessary call to getAllocatableRegClass"Tom Stellard2015-11-121-1/+7
* AMDGPU: Set isAllocatable = 0 on VS_32/VS_64Matt Arsenault2015-11-111-7/+1
* AMDGPU: Hack for VS_32 register pressureMatt Arsenault2015-11-061-4/+10
* AMDGPU: s[102:103] is unavailable on VIMatt Arsenault2015-11-031-1/+10
* AMDGPU: Define correct number of SGPRsMatt Arsenault2015-11-031-0/+4
* AMDGPU: Stop reserving v[254:255]Matt Arsenault2015-10-201-4/+0
* Make a bunch of static arrays const.Craig Topper2015-10-181-1/+1
* AMDGPU: Make SIInsertWaits about a factor of 4 fasterMatt Arsenault2015-10-011-0/+2
* AMDGPU: Switch over reg class size instead of checking all super classesMatt Arsenault2015-09-261-20/+34
* Introduce target hook for optimizing register copiesMatt Arsenault2015-09-241-0/+24
* Untabify.NAKAMURA Takumi2015-09-221-1/+1
* Reformat blank lines.NAKAMURA Takumi2015-09-221-1/+0
* AMDGPU: Remove dead codeMatt Arsenault2015-09-191-8/+0
* AMDGPU: Set mem operands for spill instructionsMatt Arsenault2015-08-291-8/+9
* AMDGPU: Make sure to reserve super registersMatt Arsenault2015-08-261-16/+15
* MachineRegisterInfo: Introduce isPhysRegUsed()Matthias Braun2015-08-181-6/+3
* AMDGPU/SI: Add missing spill classTom Stellard2015-08-141-1/+2
* AMDGPU: Remove SCCReg.Matt Arsenault2015-08-051-2/+0
* MachineRegisterInfo: Remove UsedPhysReg infrastructureMatthias Braun2015-07-141-1/+1
* R600 -> AMDGPU renameTom Stellard2015-06-131-0/+543
* Revert "AMDGPU: Add core backend files for R600/SI codegen v6"Tom Stellard2012-07-161-51/+0
* AMDGPU: Add core backend files for R600/SI codegen v6Tom Stellard2012-07-161-0/+51
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