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path: root/llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.h
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* AMDGPU: Add StackPtr and FramePtr registers to MFIMatt Arsenault2017-04-241-0/+24
* AMDGPU: Make MFI fields privateMatt Arsenault2017-04-181-3/+5
* AMDGPU: Refactor argument loweringMatt Arsenault2017-04-111-3/+10
* AMDGPU: Fix crash when disassembling VOP3 macMatt Arsenault2017-04-101-0/+1
* AMDGPU: Don't use stack space for SGPR->VGPR spillsMatt Arsenault2017-02-211-4/+22
* AMDGPU add support for spilling to a user sgpr pointed buffersTom Stellard2017-01-251-0/+17
* [AMDGPU] Fix some Clang-tidy modernize and Include What You Use warnings; oth...Eugene Zelenko2017-01-211-7/+13
* AMDGPU/SI: Make a function constTom Stellard2016-12-201-3/+3
* AMDGPU/SI: Add a MachineMemOperand when lowering llvm.amdgcn.buffer.load.*Tom Stellard2016-12-201-0/+28
* AMDGPU/SI: Add a MachineMemOperand to MIMG instructionsTom Stellard2016-12-201-0/+31
* [AMDGPU] Wave and register controlsKonstantin Zhuravlyov2016-09-061-8/+37
* AMDGPU: fix mismatch tags, NFCSaleem Abdulrasool2016-08-291-1/+1
* AMDGPU: Remove unused tracking of flat instructionsMatt Arsenault2016-08-111-9/+0
* AMDGPU: Make AMDGPUMachineFunction fields privateMatt Arsenault2016-07-261-1/+0
* AMDGPU: Add HSA dispatch id intrinsicMatt Arsenault2016-07-221-5/+6
* AMDGPU/SI: Emit the number of SGPR and VGPR spillsMarek Olsak2016-07-131-0/+19
* SIMachineFunctionInfo.cpp: Appease msc18 to use std::array.NAKAMURA Takumi2016-06-271-2/+3
* Reformat blank lines.NAKAMURA Takumi2016-06-271-1/+0
* [AMDGPU] Emit debugger prologue and emit the rest of the debugger fields in t...Konstantin Zhuravlyov2016-06-251-0/+60
* [AMDGPU][NFC] Rename ReserveTrapVGPRs -> ReserveRegsKonstantin Zhuravlyov2016-05-241-4/+5
* [AMDGPU] Move reserved vgpr count for trap handler usage to SIMachineFunction...Konstantin Zhuravlyov2016-04-261-0/+7
* AMDGPU: Implement addrspacecastMatt Arsenault2016-04-251-0/+4
* AMDGPU: allow specifying a workgroup size that needs to fit in a compute unitTom Stellard2016-04-141-0/+2
* AMDGPU/SI: Use the correct scratch wave offset register for shaders.Tom Stellard2016-04-141-0/+4
* AMDGPU: R600 code splitting cleanupMatt Arsenault2016-03-111-5/+3
* AMDGPU/SI: Add support for spiling SGPRs to scratch bufferTom Stellard2016-03-041-1/+2
* AMDGPU: Set flat_scratch from flat_scratch_init regMatt Arsenault2016-02-121-0/+19
* AMDGPU/SI: Add s_waitcnt at the end of non-void functionsMarek Olsak2016-01-131-0/+9
* AMDGPU/SI: Add new target attribute InitialPSInputAddrMarek Olsak2016-01-131-1/+16
* AMDGPU: Rework how private buffer passed for HSAMatt Arsenault2015-11-301-2/+111
* AMDGPU: Check feature attributes in SIMachineFunctionInfoMatt Arsenault2015-11-251-6/+98
* AMDGPU: Also track whether SGPRs were spilledMatt Arsenault2015-11-051-2/+17
* R600 -> AMDGPU renameTom Stellard2015-06-131-0/+66
* Revert "AMDGPU: Add core backend files for R600/SI codegen v6"Tom Stellard2012-07-161-37/+0
* AMDGPU: Add core backend files for R600/SI codegen v6Tom Stellard2012-07-161-0/+37
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