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| author | Tom Stellard <thomas.stellard@amd.com> | 2016-03-04 18:31:18 +0000 |
|---|---|---|
| committer | Tom Stellard <thomas.stellard@amd.com> | 2016-03-04 18:31:18 +0000 |
| commit | 649b5db557d5c7005e2f2ca9d893377bd733dc2e (patch) | |
| tree | ded01c957b5dbae57a0574c516cb2d0584682760 /llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.h | |
| parent | 3b8f6126ac50880a17ea71fb82c828c9dc818d81 (diff) | |
| download | bcm5719-llvm-649b5db557d5c7005e2f2ca9d893377bd733dc2e.tar.gz bcm5719-llvm-649b5db557d5c7005e2f2ca9d893377bd733dc2e.zip | |
AMDGPU/SI: Add support for spiling SGPRs to scratch buffer
Summary:
This is necessary for when we run out of VGPRs and can no
longer use v_{read,write}_lane for spilling SGPRs.
Reviewers: arsenm
Subscribers: arsenm, llvm-commits
Differential Revision: http://reviews.llvm.org/D17592
llvm-svn: 262732
Diffstat (limited to 'llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.h')
| -rw-r--r-- | llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.h | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.h b/llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.h index 787b3bb7a75..2f4e494faaf 100644 --- a/llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.h +++ b/llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.h @@ -113,8 +113,9 @@ public: unsigned VGPR; int Lane; SpilledReg(unsigned R, int L) : VGPR (R), Lane (L) { } - SpilledReg() : VGPR(0), Lane(-1) { } + SpilledReg() : VGPR(AMDGPU::NoRegister), Lane(-1) { } bool hasLane() { return Lane != -1;} + bool hasReg() { return VGPR != AMDGPU::NoRegister;} }; // SIMachineFunctionInfo definition |
