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authorEugene Zelenko <eugene.zelenko@gmail.com>2017-01-21 00:53:49 +0000
committerEugene Zelenko <eugene.zelenko@gmail.com>2017-01-21 00:53:49 +0000
commit6620376da79f7ee91f71cf93c5921fb8f406f71c (patch)
tree537aaf909aff9419823eda234af085c2c13b97b4 /llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.h
parent8f470db6729f127ee9c3a6f46e9298690e9e6c32 (diff)
downloadbcm5719-llvm-6620376da79f7ee91f71cf93c5921fb8f406f71c.tar.gz
bcm5719-llvm-6620376da79f7ee91f71cf93c5921fb8f406f71c.zip
[AMDGPU] Fix some Clang-tidy modernize and Include What You Use warnings; other minor fixes (NFC).
llvm-svn: 292688
Diffstat (limited to 'llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.h')
-rw-r--r--llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.h20
1 files changed, 13 insertions, 7 deletions
diff --git a/llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.h b/llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.h
index 3b4e233cd78..2d92068e5c4 100644
--- a/llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.h
+++ b/llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.h
@@ -16,13 +16,16 @@
#include "AMDGPUMachineFunction.h"
#include "SIRegisterInfo.h"
+#include "llvm/CodeGen/PseudoSourceValue.h"
+#include "llvm/MC/MCRegisterInfo.h"
+#include "llvm/Support/ErrorHandling.h"
#include <array>
+#include <cassert>
#include <map>
+#include <utility>
namespace llvm {
-class MachineRegisterInfo;
-
class AMDGPUImagePseudoSourceValue : public PseudoSourceValue {
public:
explicit AMDGPUImagePseudoSourceValue() :
@@ -174,10 +177,12 @@ private:
public:
struct SpilledReg {
- unsigned VGPR;
- int Lane;
+ unsigned VGPR = AMDGPU::NoRegister;
+ int Lane = -1;
+
+ SpilledReg() = default;
SpilledReg(unsigned R, int L) : VGPR (R), Lane (L) { }
- SpilledReg() : VGPR(AMDGPU::NoRegister), Lane(-1) { }
+
bool hasLane() { return Lane != -1;}
bool hasReg() { return VGPR != AMDGPU::NoRegister;}
};
@@ -185,6 +190,7 @@ public:
// SIMachineFunctionInfo definition
SIMachineFunctionInfo(const MachineFunction &MF);
+
SpilledReg getSpilledReg(MachineFunction *MF, unsigned FrameIndex,
unsigned SubIdx);
bool hasCalculatedTID() const { return TIDReg != AMDGPU::NoRegister; };
@@ -495,6 +501,6 @@ public:
}
};
-} // End namespace llvm
+} // end namespace llvm
-#endif
+#endif // LLVM_LIB_TARGET_AMDGPU_SIMACHINEFUNCTIONINFO_H
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