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path: root/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
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* AMDGPU: Use generic bitreverse intrinsicMatt Arsenault2015-12-141-0/+1
* AMDGPU/SI: Emit constant arrays in the .text sectionTom Stellard2015-12-101-13/+1
* AMDGPU/SI: Add support for sgpr and vgpr inline assembly constraintsTom Stellard2015-12-101-6/+47
* AMDGPU: Implement isNoopAddrSpaceCastMatt Arsenault2015-12-011-0/+11
* AMDGPU/SI: Remove REGISTER_STORE/REGISTER_LOAD code which is now deadTom Stellard2015-12-011-16/+0
* AMDGPU: Fix unused functionMatt Arsenault2015-11-301-5/+0
* AMDGPU: Rework how private buffer passed for HSAMatt Arsenault2015-11-301-32/+128
* AMDGPU: Rename enums to be consistent with HSA code object terminologyMatt Arsenault2015-11-301-16/+10
* AMDGPU: Remove SIPrepareScratchRegsMatt Arsenault2015-11-301-11/+6
* AMDGPU: Use assert zext for workgroup sizesMatt Arsenault2015-11-301-10/+21
* AMDGPU: Don't reserve SCRATCH_PTR input registerMatt Arsenault2015-11-301-12/+4
* AMDGPU: Add llvm.amdgcn.dispatch.ptr intrinsicTom Stellard2015-11-261-0/+16
* AMDGPU: Make v2i64/v2f64 legal types.Matt Arsenault2015-11-251-1/+43
* AMDGPU: Split LDS vector loadsMatt Arsenault2015-11-241-1/+2
* AMDGPU: Split x8 and x16 vector loads instead of scalarizeMatt Arsenault2015-11-241-1/+5
* AMDGPU: Error on graphics shaders with HSAMatt Arsenault2015-11-021-0/+8
* AMDGPU/SI: handle undef for llvm.SI.packf16Marek Olsak2015-10-291-0/+4
* AMDGPU: Simplify VOP3 operand legalization.Matt Arsenault2015-10-211-1/+6
* AMDGPU: Add MachineInstr overloads for instruction format testsMatt Arsenault2015-10-201-1/+1
* AMDGPU/SI: Remove calling convention assertion from LowerFormalArguments()Tom Stellard2015-10-061-1/+1
* AMDGPU/SI: Don't set DATA_FORMAT if ADD_TID_ENABLE is setMarek Olsak2015-09-291-3/+1
* AMDGPU: Re-justify workaround and fix worked around problemMatt Arsenault2015-09-251-38/+23
* Reformat comment lines.NAKAMURA Takumi2015-09-221-1/+1
* Use makeArrayRef or None to avoid unnecessarily mentioning the ArrayRef type ...Craig Topper2015-09-211-1/+1
* propagate fast-math-flags on DAG nodesSanjay Patel2015-09-161-1/+8
* SelectionDAG: Support Expand of f16 extloadsMatt Arsenault2015-09-091-29/+3
* check for fastness before merging in DAGCombiner::MergeConsecutiveStores() Sanjay Patel2015-09-031-1/+4
* Fix some comment typos.Benjamin Kramer2015-08-081-5/+5
* AMDGPU: Assume SMRD access for constant address spaceMatt Arsenault2015-08-071-40/+75
* De-constify pointers to Type since they can't be modified. NFCCraig Topper2015-08-011-1/+1
* AMDGPU: Fix v16i32 to v16i8 truncstoreMatt Arsenault2015-07-311-0/+1
* AMDGPU/SI: Add VI patterns to select FLAT instructions for global memory opsTom Stellard2015-07-201-6/+23
* AMDPGU/SI: Use AssertZext node to mask high bit for scratch offsetsTom Stellard2015-07-161-2/+28
* AMDGPU: Fix chains for memory ops dependent on argument loadsMatt Arsenault2015-07-101-4/+19
* AMDGPU: Use requested chain when lowering argumentsMatt Arsenault2015-07-101-1/+1
* AMDGPU: Add helper function for implicit parameter offsets.Tom Stellard2015-07-091-2/+2
* Re-instate the EVT parameter to getScalarShiftAmountTy() for OOT userMehdi Amini2015-07-091-1/+1
* Remove getDataLayout() from TargetLoweringMehdi Amini2015-07-091-4/+4
* Make isLegalAddressingMode() taking DataLayout as an argumentMehdi Amini2015-07-091-2/+3
* Make TargetLowering::getShiftAmountTy() taking DataLayout as an argumentMehdi Amini2015-07-091-1/+1
* Make TargetLowering::getPointerTy() taking DataLayout as an argumentMehdi Amini2015-07-091-5/+7
* [TargetLowering] StringRefize asm constraint getters.Benjamin Kramer2015-07-051-2/+1
* AMDGPU/SI: There are no implicit kernel args in the amdhsa ABITom Stellard2015-06-261-1/+2
* AMDGPU: Use getAsInteger instead of atoiMatt Arsenault2015-06-231-3/+5
* R600 -> AMDGPU renameTom Stellard2015-06-131-0/+2241
* Revert "AMDGPU: Add core backend files for R600/SI codegen v6"Tom Stellard2012-07-161-195/+0
* AMDGPU: Add core backend files for R600/SI codegen v6Tom Stellard2012-07-161-0/+195
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