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path: root/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
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* AMDGPU: Implement canonicalizeMatt Arsenault2016-04-141-0/+43
* AMDGPU: Eliminate half of i64 or if one operand is zero_extend from i32Matt Arsenault2016-04-121-0/+30
* AMDGPU: Add atomic_inc + atomic_dec intrinsicsMatt Arsenault2016-04-121-1/+48
* AMDGPU: Add a shader calling conventionNicolai Haehnle2016-04-061-9/+8
* AMDGPU: Implement {BUFFER,FLAT}_ATOMIC_CMPSWAP{,_X2}Tom Stellard2016-04-011-0/+62
* AMDGPU/SI: Implement GroupStaticSize Intrinsic for Dynamic LDSChangpeng Fang2016-03-151-2/+14
* AMDGPU: More bits of frame index are known to be zeroMatt Arsenault2016-02-271-15/+25
* AMDGPU: Implement readcyclecounterMatt Arsenault2016-02-271-0/+3
* [AMDGPU] Assembler: Basic support for MIMGNikolay Haustov2016-02-261-3/+6
* AMDGPU/SI: add llvm.amdgcn.image.load/store[.mip] intrinsicsNicolai Haehnle2016-02-181-3/+4
* AMDGPU: Prepare for reducing private element size.Matt Arsenault2016-02-131-14/+48
* AMDGPU: Add intrinsics for sin/cosMatt Arsenault2016-02-131-0/+16
* AMDGPU: Rename intrinsic to better match instruction nameMatt Arsenault2016-02-131-2/+2
* AMDGPU: Fix broken condition causing warningMatt Arsenault2016-02-131-1/+1
* AMDGPU/SI: Detect uniform branches and emit s_cbranch instructionsTom Stellard2016-02-121-5/+33
* AMDGPU: Set flat_scratch from flat_scratch_init regMatt Arsenault2016-02-121-1/+10
* AMDGPU: Split R600 and SI store loweringMatt Arsenault2016-02-111-13/+17
* AMDGPU: Fix indentation and variable namesMatt Arsenault2016-02-101-34/+31
* AMDGPU: Split R600 and SI load loweringMatt Arsenault2016-02-101-1/+23
* [CodeGen] Prefer "if (SDValue R = ...)" to "if (R.getNode())". NFCI.Ahmed Bougacha2016-02-091-4/+2
* Refactor backend diagnostics for unsupported featuresOliver Stannard2016-02-021-4/+6
* AMDGPU: Fix emitting invalid workitem intrinsics for HSAMatt Arsenault2016-01-301-0/+34
* AMDGPU: Add new amdgcn workitem intrinsicsMatt Arsenault2016-01-301-0/+6
* AMDGPU: Match fmed3 patterns with legacy fmin/fmaxMatt Arsenault2016-01-281-26/+32
* AMDGPU: Match some med3 patternsMatt Arsenault2016-01-281-5/+88
* Revert r259035, it introduces a cyclic library dependencyOliver Stannard2016-01-281-6/+4
* Add backend dignostic printer for unsupported featuresOliver Stannard2016-01-281-4/+6
* Revert r258951 (and r258950), "Refactor backend diagnostics for unsupported f...NAKAMURA Takumi2016-01-281-6/+4
* Refactor backend diagnostics for unsupported featuresOliver Stannard2016-01-271-4/+6
* AMDGPU: Make v32i8/v64i8 illegal typesMatt Arsenault2016-01-261-3/+0
* AMDGPU: Remove old sample intrinsicsMatt Arsenault2016-01-261-17/+0
* AMDGPU: Implement read_register and write_register intrinsicsMatt Arsenault2016-01-261-0/+47
* AMDGPU: Restore AMDGPU prefixed rsq intrinsic for nowMatt Arsenault2016-01-261-1/+2
* AMDGPU: Move amdgcn intrinsic handling into SITargetLoweringMatt Arsenault2016-01-231-1/+66
* AMDGPU: Rename intrinsics to use amdgcn prefixMatt Arsenault2016-01-221-1/+2
* AMDGPU: Remove AMDGPU.fract intrinsicMatt Arsenault2016-01-221-3/+0
* AMDGPU/SI: Promote i1 SETCC operationsTom Stellard2016-01-201-0/+1
* AMDGPU: Remove AMDIL.fraction intrinsicMatt Arsenault2016-01-201-2/+1
* AMDGPU/SI: Prevent the DAGCombiner from creating setcc with i1 inputsTom Stellard2016-01-201-0/+10
* AMDGPU: Split 64-bit and of constant upMatt Arsenault2016-01-181-0/+3
* AMDGPU/SI: Fix a GPU hang with POS_W_FLOAT enabledMarek Olsak2016-01-131-1/+8
* AMDGPU/SI: Add s_waitcnt at the end of non-void functionsMarek Olsak2016-01-131-0/+2
* AMDGPU/SI: Add support for non-void functionsMarek Olsak2016-01-131-0/+89
* AMDGPU/SI: Allow any number of PS inputsMarek Olsak2016-01-131-3/+1
* AMDGPU/SI: Add new target attribute InitialPSInputAddrMarek Olsak2016-01-131-4/+15
* AMDGPU: Fix crash with dispatch.ptr intrinsic with non-HSA targetMatt Arsenault2016-01-111-0/+7
* AMDGPU: Pattern match ffbh pattern to instruction.Matt Arsenault2016-01-111-2/+1
* AMDGPU: Remove dead target dag combineMatt Arsenault2016-01-111-1/+0
* AMDGPU/SI: Select constant loads with non-uniform addresses to MUBUF instruct...Tom Stellard2015-12-151-0/+23
* AMDGPU/SI: Add llvm.amdgcn.v.interp.p[12] intrinsicsTom Stellard2015-12-151-0/+13
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