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* Revert "[AMDGPU] Kernel arg metadata: added support for "__hip_texture" type."Matt Arsenault2019-07-031-10/+0
* [AMDGPU] Kernel arg metadata: added support for "__hip_texture" type.Konstantin Pyzhov2019-07-031-0/+10
* [AMDGPU] Enable serializing of argument info.Michael Liao2019-07-033-1/+253
* AMDGPU: Look through bundles for existing waitcntsMatt Arsenault2019-07-031-1/+2
* AMDGPU: Custom lower vector_shuffle for v4i16/v4f16Matt Arsenault2019-07-022-0/+63
* [AMDGPU] LCSSA pass added in preISel. Fixing typo in previous commitAlexander Timofeev2019-07-021-1/+1
* [AMDGPU] LCSSA pass added in preISel. Uniform values defined in the divergent...Alexander Timofeev2019-07-022-0/+19
* AMDGPU/GlobalISel: Try generated matcher with intrinsicsMatt Arsenault2019-07-021-8/+7
* AMDGPU/GlobalISel: Select mulMatt Arsenault2019-07-021-1/+1
* AMDGPU/GlobalISel: Fix G_GEP with mixed SGPR/VGPR operandsMatt Arsenault2019-07-021-4/+6
* AMDGPU/GlobalISel: Select G_FENCEMatt Arsenault2019-07-021-0/+5
* AMDGPU: Correct properties for adjcallstack* pseudosMatt Arsenault2019-07-011-0/+4
* AMDGPU/GlobalISel: Handle more input argument intrinsicsMatt Arsenault2019-07-012-41/+72
* AMDGPU/GlobalISel: Lower kernarg segment ptr intrinsicsMatt Arsenault2019-07-013-24/+48
* AMDGPU/GlobalISel: Legalize workgroup ID intrinsicsMatt Arsenault2019-07-012-0/+36
* AMDGPU/GlobalISel: Legalize workitem ID intrinsicsMatt Arsenault2019-07-013-0/+127
* AMDGPU/GlobalISel: Custom lower control flow intrinsicsMatt Arsenault2019-07-012-0/+68
* AMDGPU/GlobalISel: Handle 16-bit SALU min/maxMatt Arsenault2019-07-011-5/+19
* AMDGPU/GlobalISel: Lower SALU min/max to cmp+selectMatt Arsenault2019-07-011-6/+41
* AMDGPU/GlobalISel: Legalize s16 add/sub/mulMatt Arsenault2019-07-012-2/+85
* AMDGPU/GlobalISel: Fix allowing non-boolean conditions for G_SELECTMatt Arsenault2019-07-011-9/+20
* AMDGPU/GlobalISel: RegBankSelect for sendmsg/sendmsghaltMatt Arsenault2019-07-011-3/+29
* AMDGPU/GlobalISel: Legalize s16 fcmpMatt Arsenault2019-07-011-1/+9
* AMDGPU/GFX10: implement ds_ordered_count changesNicolai Haehnle2019-07-011-1/+22
* AMDGPU: Support GDS atomicsNicolai Haehnle2019-07-018-54/+97
* AMDGPU/GlobalISel: RegBankSelect for DS ordered add/swapMatt Arsenault2019-07-011-2/+31
* AMDGPU/GlobalISel: RegBankSelect for amdgcn.writelaneMatt Arsenault2019-07-011-5/+58
* AMDGPU/GlobalISel: Fail instead of assert when selecting loadsMatt Arsenault2019-07-011-5/+11
* AMDGPU/GlobalISel: Complete implementation of G_GEPMatt Arsenault2019-07-013-53/+79
* AMDGPU/GlobalISel: Select G_PHIMatt Arsenault2019-07-012-0/+41
* AMDGPU/GlobalISel: Try to select VOP3 form of addMatt Arsenault2019-07-011-0/+20
* AMDGPU/GlobalISel: RegBankSelect for readlane/readfirstlaneMatt Arsenault2019-07-012-0/+82
* AMDGPU/GlobalISel: Implement select for 32-bit G_ADDTom Stellard2019-07-012-2/+7
* AMDGPU/GlobalISel: Select G_BRCOND for vccMatt Arsenault2019-07-012-25/+44
* AMDGPU/GlobalISel: Select G_FRAME_INDEXMatt Arsenault2019-07-012-0/+19
* AMDGPU/GFX10: fix scratch resource descriptorNicolai Haehnle2019-07-011-2/+2
* AMDGPU/GlobalISel: Make s16 select legalMatt Arsenault2019-07-012-7/+9
* AMDGPU/GlobalISel: Select G_BRCOND for scc conditionsMatt Arsenault2019-07-012-0/+34
* AMDGPU/GlobalISel: Tolerate copies with no type setMatt Arsenault2019-07-011-3/+6
* AMDGPU/GlobalISel: Select src modifiersMatt Arsenault2019-07-012-6/+43
* AMDGPU: Convert some places to RegisterMatt Arsenault2019-07-012-9/+10
* AMDGPU/GlobalISel: Fix RegBankSelect for G_FCANONICALIZEMatt Arsenault2019-07-011-0/+1
* AMDGPU/GlobalISel: Fix RegBankSelect for G_BUILD_VECTORMatt Arsenault2019-07-011-1/+2
* AMDGPU/GlobalISel: Fail on store to 32-bit address spaceMatt Arsenault2019-07-011-0/+6
* AMDGPU/GlobalISel: Improve icmp selection coverage.Matt Arsenault2019-07-012-13/+38
* AMDGPU/GlobalISel: RegBankSelect for WWM/WQMMatt Arsenault2019-07-011-0/+2
* AMDGPU/GlobalISel: Use vcc reg bank for amdgcn.wqm.voteMatt Arsenault2019-07-011-1/+1
* AMDGPU/GlobalISel: Fix scc->vcc copy handlingMatt Arsenault2019-07-012-13/+23
* AMDGPU/GlobalISel: Use and instead of BFE with inline immediateMatt Arsenault2019-07-011-6/+29
* [AMDGPU] Call isLoopExiting for blocks in the loop.Florian Hahn2019-07-011-2/+4
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