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authorMatt Arsenault <Matthew.Arsenault@amd.com>2015-11-24 12:05:03 +0000
committerMatt Arsenault <Matthew.Arsenault@amd.com>2015-11-24 12:05:03 +0000
commit4d801cd357c74bb7c2a60fedf4030b9fb5b4827f (patch)
treeab89b79da213d3d358dbdaf7b6ba19ba2fe2d994 /llvm/lib/Target/AMDGPU/SIISelLowering.cpp
parent9d0f44bf8af57cbe992edada1a5351881b1388b2 (diff)
downloadbcm5719-llvm-4d801cd357c74bb7c2a60fedf4030b9fb5b4827f.tar.gz
bcm5719-llvm-4d801cd357c74bb7c2a60fedf4030b9fb5b4827f.zip
AMDGPU: Split x8 and x16 vector loads instead of scalarize
The one regression in the builtin tests is in the read2 test which now (again) has many extra copies, but this should be solved once the pass is replaced with a DAG combine. llvm-svn: 253974
Diffstat (limited to 'llvm/lib/Target/AMDGPU/SIISelLowering.cpp')
-rw-r--r--llvm/lib/Target/AMDGPU/SIISelLowering.cpp6
1 files changed, 5 insertions, 1 deletions
diff --git a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
index 0c5c10486ae..5aed57b4b4d 100644
--- a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+++ b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
@@ -1178,10 +1178,14 @@ SDValue SITargetLowering::LowerLOAD(SDValue Op, SelectionDAG &DAG) const {
"Custom lowering for non-i32 vectors hasn't been implemented.");
unsigned NumElements = Op.getValueType().getVectorNumElements();
assert(NumElements != 2 && "v2 loads are supported for all address spaces.");
+
switch (Load->getAddressSpace()) {
default: break;
case AMDGPUAS::GLOBAL_ADDRESS:
case AMDGPUAS::PRIVATE_ADDRESS:
+ if (NumElements >= 8)
+ return SplitVectorLoad(Op, DAG);
+
// v4 loads are supported for private and global memory.
if (NumElements <= 4)
break;
@@ -1409,7 +1413,7 @@ SDValue SITargetLowering::LowerSTORE(SDValue Op, SelectionDAG &DAG) const {
return Ret;
if (VT.isVector() && VT.getVectorNumElements() >= 8)
- return ScalarizeVectorStore(Op, DAG);
+ return SplitVectorStore(Op, DAG);
if (VT == MVT::i1)
return DAG.getTruncStore(Store->getChain(), DL,
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