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path: root/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
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* Re-commit: [AMDGPU] Use S_DENORM_MODE for gfx10Austin Kerbow2019-08-061-14/+47
* Revert "[AMDGPU] Use S_DENORM_MODE for gfx10"Dmitri Gribenko2019-08-051-47/+14
* [AMDGPU] Use S_DENORM_MODE for gfx10Austin Kerbow2019-08-051-14/+47
* AMDGPU: Correct behavior of f16 buffer loadsMatt Arsenault2019-08-051-43/+56
* AMDGPU: Correct behavior of f16/i16 non-format store intrinsicsMatt Arsenault2019-08-051-30/+59
* [LLVM][Alignment] Introduce Alignment TypeGuillaume Chatelet2019-08-051-6/+6
* AMDGPU: add missing llvm.amdgcn.{raw,struct}.buffer.atomic.{inc,dec}Nicolai Haehnle2019-08-051-2/+18
* Finish moving TargetRegisterInfo::isVirtualRegister() and friends to llvm::Re...Daniel Sanders2019-08-011-3/+3
* AMDGPU: Remove v0 workaround for DS_GWS_* instructionsMatt Arsenault2019-08-011-15/+3
* AMDGPU: Use tablegen pattern for sendmsg intrinsicsMatt Arsenault2019-08-011-9/+0
* [AMDGPU] Reserve all AGPRs on targets which do not have themStanislav Mekhanoshin2019-07-301-0/+2
* [AMDGPU] Enable v4f16 and above for v_pk_fma instructionsDavid Stuttard2019-07-291-0/+27
* [AMDGPU] Move WQM/WWM intrinsic instruction selection to AMDGPUISelDAGToDAGCarl Ritson2019-07-261-10/+0
* AMDGPU: Don't assert on v4f16 arguments to shader calling conventionsMatt Arsenault2019-07-251-1/+2
* AMDGPU: Force s_waitcnt after GWS instructionsMatt Arsenault2019-07-191-3/+20
* AMDGPU/GlobalISel: Rewrite lowerFormalArgumentsMatt Arsenault2019-07-191-29/+36
* AMDGPU: Decompose all values to 32-bit pieces for calling conventionsMatt Arsenault2019-07-191-11/+18
* [AMDGPU] Change register type for v32 vectorsStanislav Mekhanoshin2019-07-161-2/+2
* AMDGPU: Add 24-bit mul intrinsicsMatt Arsenault2019-07-151-0/+5
* [AMDGPU] use v32f32 for 3 mfma intrinsicsStanislav Mekhanoshin2019-07-121-2/+4
* AMDGPU: Drop remnants of byval support for shadersMatt Arsenault2019-07-121-2/+1
* [AMDGPU] gfx908 mfma supportStanislav Mekhanoshin2019-07-111-0/+34
* [AMDGPU] gfx908 atomic fadd and atomic pk_faddStanislav Mekhanoshin2019-07-111-0/+70
* [AMDGPU] gfx908 mAI instructions, MC partStanislav Mekhanoshin2019-07-091-0/+26
* [AMDGPU] Created a sub-register class for the return address operand in the r...Christudasan Devadasan2019-07-091-9/+6
* AMDGPU: Make s34 the FP registerMatt Arsenault2019-07-081-17/+0
* [AMDGPU] Custom lower INSERT_SUBVECTOR v3, v4, v5, v8Tim Renouf2019-07-041-8/+36
* AMDGPU: Custom lower vector_shuffle for v4i16/v4f16Matt Arsenault2019-07-021-0/+62
* AMDGPU/GFX10: implement ds_ordered_count changesNicolai Haehnle2019-07-011-1/+22
* AMDGPU: Support GDS atomicsNicolai Haehnle2019-07-011-3/+3
* [AMDGPU] Packed thread ids in function call ABIStanislav Mekhanoshin2019-06-281-11/+86
* AMDGPU: Write LDS objects out as global symbols in code generationNicolai Haehnle2019-06-251-2/+24
* AMDGPU: Fix not using s33 for scratch wave offset in kernelsMatt Arsenault2019-06-211-7/+11
* AMDGPU: Always use s33 for global scratch wave offsetMatt Arsenault2019-06-201-8/+0
* AMDGPU: Add intrinsics for DS GWS semaphore instructionsMatt Arsenault2019-06-201-4/+7
* AMDGPU: Insert mem_viol check loop around GWS pre-GFX9Matt Arsenault2019-06-201-18/+114
* AMDGPU: Consolidate some getGeneration checksMatt Arsenault2019-06-191-9/+6
* Reapply "AMDGPU: Add ds_gws_init / ds_gws_barrier intrinsics"Matt Arsenault2019-06-191-0/+18
* Revert rL363678 : AMDGPU: Add ds_gws_init / ds_gws_barrier intrinsicsSimon Pilgrim2019-06-191-18/+0
* AMDGPU: Add ds_gws_init / ds_gws_barrier intrinsicsMatt Arsenault2019-06-181-0/+18
* AMDGPU: Be explicit about whether the high-word in SI_PC_ADD_REL_OFFSET is 0Nicolai Haehnle2019-06-161-5/+12
* AMDGPU/GFX10: Support DLC bit in llvm.amdgcn.s.buffer.load intrinsicNicolai Haehnle2019-06-161-5/+11
* [AMDGPU] gfx10 conditional registers handlingStanislav Mekhanoshin2019-06-161-24/+78
* [AMDGPU] gfx1010 wave32 icmp/fcmp intrinsic changes for wave32Stanislav Mekhanoshin2019-06-131-5/+27
* [AMDGPU] gfx1010 premlane instructionsStanislav Mekhanoshin2019-06-121-0/+18
* [TargetLowering] Add MachineMemOperand::Flags to allowsMemoryAccess tests (PR...Simon Pilgrim2019-06-121-4/+3
* [TargetLowering] Add allowsMemoryAccess(MachineMemOperand) helper wrapper. NFCI.Simon Pilgrim2019-06-111-5/+6
* [AMDGPU] Optimize image_[load|store]_mipPiotr Sobczak2019-06-101-0/+13
* [AMDGPU] Partial revert for the ba447bae7448435c9986eece0811da1423972fddAlexander Timofeev2019-06-061-87/+0
* AMDGPU: Don't fix emergency stack slot at offset 0Matt Arsenault2019-06-051-10/+0
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