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| author | Stanislav Mekhanoshin <Stanislav.Mekhanoshin@amd.com> | 2019-07-12 22:42:01 +0000 |
|---|---|---|
| committer | Stanislav Mekhanoshin <Stanislav.Mekhanoshin@amd.com> | 2019-07-12 22:42:01 +0000 |
| commit | 1dfae6fe505ffedf97e9f36d207cb8bbdc9255d8 (patch) | |
| tree | 2d950113da5ca558c53c071b4c41b2e46f2e09f4 /llvm/lib/Target/AMDGPU/SIISelLowering.cpp | |
| parent | b1bff76e22bd39eb46dcae49891fda1cf1cc0bd5 (diff) | |
| download | bcm5719-llvm-1dfae6fe505ffedf97e9f36d207cb8bbdc9255d8.tar.gz bcm5719-llvm-1dfae6fe505ffedf97e9f36d207cb8bbdc9255d8.zip | |
[AMDGPU] use v32f32 for 3 mfma intrinsics
These should really use v32f32, but were defined as v32i32
due to the lack of the v32f32 type.
Differential Revision: https://reviews.llvm.org/D64667
llvm-svn: 365972
Diffstat (limited to 'llvm/lib/Target/AMDGPU/SIISelLowering.cpp')
| -rw-r--r-- | llvm/lib/Target/AMDGPU/SIISelLowering.cpp | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp index 3eb1b1c9106..b90a0d28e9e 100644 --- a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp +++ b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp @@ -153,6 +153,7 @@ SITargetLowering::SITargetLowering(const TargetMachine &TM, if (Subtarget->hasMAIInsts()) { addRegisterClass(MVT::v32i32, &AMDGPU::AReg_1024RegClass); + addRegisterClass(MVT::v32f32, &AMDGPU::AReg_1024RegClass); } computeRegisterProperties(Subtarget->getRegisterInfo()); @@ -263,8 +264,9 @@ SITargetLowering::SITargetLowering(const TargetMachine &TM, // We only support LOAD/STORE and vector manipulation ops for vectors // with > 4 elements. - for (MVT VT : {MVT::v8i32, MVT::v8f32, MVT::v16i32, MVT::v16f32, - MVT::v2i64, MVT::v2f64, MVT::v4i16, MVT::v4f16, MVT::v32i32 }) { + for (MVT VT : { MVT::v8i32, MVT::v8f32, MVT::v16i32, MVT::v16f32, + MVT::v2i64, MVT::v2f64, MVT::v4i16, MVT::v4f16, + MVT::v32i32, MVT::v32f32 }) { for (unsigned Op = 0; Op < ISD::BUILTIN_OP_END; ++Op) { switch (Op) { case ISD::LOAD: |
