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| author | Stanislav Mekhanoshin <Stanislav.Mekhanoshin@amd.com> | 2019-07-30 19:29:33 +0000 |
|---|---|---|
| committer | Stanislav Mekhanoshin <Stanislav.Mekhanoshin@amd.com> | 2019-07-30 19:29:33 +0000 |
| commit | 450afcea39edd897eed541527e5150a9063397dd (patch) | |
| tree | e50824032ce10b90ce7ac6a24aca2620feef5320 /llvm/lib/Target/AMDGPU/SIISelLowering.cpp | |
| parent | be19c48f6d6b7dd8e4c94dc15eba6963fa22fd10 (diff) | |
| download | bcm5719-llvm-450afcea39edd897eed541527e5150a9063397dd.tar.gz bcm5719-llvm-450afcea39edd897eed541527e5150a9063397dd.zip | |
[AMDGPU] Reserve all AGPRs on targets which do not have them
Differential Revision: https://reviews.llvm.org/D65471
llvm-svn: 367347
Diffstat (limited to 'llvm/lib/Target/AMDGPU/SIISelLowering.cpp')
| -rw-r--r-- | llvm/lib/Target/AMDGPU/SIISelLowering.cpp | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp index 2a69b2ebb60..fa0dc7787e8 100644 --- a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp +++ b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp @@ -10464,6 +10464,8 @@ SITargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, } break; case 'a': + if (!Subtarget->hasMAIInsts()) + break; switch (VT.getSizeInBits()) { default: return std::make_pair(0U, nullptr); |
