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author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2019-06-18 13:19:57 +0000 |
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committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2019-06-18 13:19:57 +0000 |
commit | 8d35dcd70395deb0ffebca35afffd0ad076e27ca (patch) | |
tree | b9ee3e09ef65c89348992b00b8d44a6ba186b797 /llvm/lib/Target/AMDGPU/SIISelLowering.cpp | |
parent | 3b2f5df12c886674d592c6ce1aa51d418e95b751 (diff) | |
download | bcm5719-llvm-8d35dcd70395deb0ffebca35afffd0ad076e27ca.tar.gz bcm5719-llvm-8d35dcd70395deb0ffebca35afffd0ad076e27ca.zip |
AMDGPU: Add ds_gws_init / ds_gws_barrier intrinsics
There may or may not be additional work to handle this correctly on
SI/CI.
llvm-svn: 363678
Diffstat (limited to 'llvm/lib/Target/AMDGPU/SIISelLowering.cpp')
-rw-r--r-- | llvm/lib/Target/AMDGPU/SIISelLowering.cpp | 18 |
1 files changed, 18 insertions, 0 deletions
diff --git a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp index 80acf5783ad..54cc459e148 100644 --- a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp +++ b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp @@ -961,6 +961,24 @@ bool SITargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info, return true; } + case Intrinsic::amdgcn_ds_gws_init: + case Intrinsic::amdgcn_ds_gws_barrier: { + Info.opc = ISD::INTRINSIC_VOID; + + SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>(); + Info.ptrVal = + MFI->getGWSPSV(*MF.getSubtarget<GCNSubtarget>().getInstrInfo()); + + // This is an abstract access, but we need to specify a type and size. + Info.memVT = MVT::i32; + Info.size = 4; + Info.align = 4; + + Info.flags = MachineMemOperand::MOStore; + if (IntrID == Intrinsic::amdgcn_ds_gws_barrier) + Info.flags = MachineMemOperand::MOLoad; + return true; + } default: return false; } |