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path: root/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
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* AMDGPU/SI: Move some ISel helpers into utils so they can be shared with GISelTom Stellard2017-01-271-11/+1
* AMDGPU add support for spilling to a user sgpr pointed buffersTom Stellard2017-01-251-4/+14
* AMDGPU : Add trap handler support.Wei Ding2017-01-241-19/+24
* AMDGPU: Custom lower more vector operationsMatt Arsenault2017-01-231-0/+100
* AMDGPU: Remove unnecessary checkMatt Arsenault2017-01-231-3/+0
* [AMDGPU] Fix some Clang-tidy modernize and Include What You Use warnings; oth...Eugene Zelenko2017-01-211-38/+63
* AMDGPU: Add replacement export intrinsicsMatt Arsenault2017-01-171-9/+58
* Apply clang-tidy's performance-unnecessary-value-param to LLVM.Benjamin Kramer2017-01-131-5/+8
* [CodeGen] Rename MachineInstrBuilder::addOperand. NFCDiana Picus2017-01-131-28/+27
* AMDGPU: Add Assert[SZ]Ext during argument load creationMatt Arsenault2017-01-091-12/+15
* AMDGPU/R600: Don't use REGISTER_{LOAD,STORE} ISD nodesJan Vesely2017-01-061-0/+12
* AMDGPU/SI: Implement sendmsghalt intrinsicJan Vesely2017-01-041-1/+8
* AMDGPU: Use i16 for i16 shift amountMatt Arsenault2016-12-221-2/+4
* AMDGPU: Use i16 comparison instructionsMatt Arsenault2016-12-221-3/+1
* AMDGPU: Swap order of operands in fadd/fsub combineMatt Arsenault2016-12-221-4/+4
* AMDGPU: Check fast math flags in fadd/fsub combinesMatt Arsenault2016-12-221-6/+13
* AMDGPU: Form more FMAs if fusion is allowedMatt Arsenault2016-12-221-30/+45
* AMDGPU: Move combines into separate functionsMatt Arsenault2016-12-221-152/+169
* AMDGPU: Enable some f32 fadd/fsub combines for f16Matt Arsenault2016-12-221-7/+12
* AMDGPU: Implement isFMAFasterThanFMulAndFAdd for f16Matt Arsenault2016-12-221-0/+2
* AMDGPU: Allow rcp and rsq usage with f16Matt Arsenault2016-12-221-3/+8
* AMDGPU: Custom lower f16 fdivMatt Arsenault2016-12-221-1/+21
* AMDGPU: Implement f16 fcanonicalizeMatt Arsenault2016-12-221-0/+3
* AMDGPU: Allow 16-bit types in inline asm constraintsMatt Arsenault2016-12-201-0/+2
* AMDGPU/SI: Add a MachineMemOperand when lowering llvm.amdgcn.buffer.load.*Tom Stellard2016-12-201-0/+26
* AMDGPU/SI: Add a MachineMemOperand to MIMG instructionsTom Stellard2016-12-201-6/+24
* AMDGPU: Select branch on undef to uniform scc branchMatt Arsenault2016-12-151-0/+9
* Fix for regression after Global Load Scalarization patchAlexander Timofeev2016-12-151-1/+2
* AMDGPU: Fix isTypeDesirableForOp for i16Matt Arsenault2016-12-091-4/+16
* AMDGPU: Make f16 ConstantFP legalMatt Arsenault2016-12-081-13/+1
* [AMDGPU] Scalarization of global uniform loads.Alexander Timofeev2016-12-081-2/+17
* AMDGPU : Add S_SETREG instructions to fix fdiv precision issues.Tom Stellard2016-12-071-11/+101
* AMDGPU: Add llvm.amdgcn.interp.mov intrinsicTom Stellard2016-12-061-0/+6
* AMDGPU: Refactor exp instructionsMatt Arsenault2016-12-051-0/+23
* AMDGPU: Implement isCheapAddrSpaceCastMatt Arsenault2016-12-021-2/+12
* AMDGPU: Use SGPR_64 for argument loweringsMatt Arsenault2016-11-291-7/+7
* AMDGPU/SI: Use float as the operand type for amdgcn.interp intrinsicsTom Stellard2016-11-261-0/+2
* AMDGPU/SI: Add back reverted SGPR spilling code, but disable itMarek Olsak2016-11-251-11/+11
* Revert "AMDGPU: Make m0 unallocatable"Marek Olsak2016-11-251-11/+11
* AMDGPU: Make m0 unallocatableMatt Arsenault2016-11-241-11/+11
* AMDGPU: Fix unused variable warningMatt Arsenault2016-11-181-5/+4
* AMDGPU: Fix crash on illegal type for inlineasmMatt Arsenault2016-11-181-0/+2
* [AMDGPU] Custom lower f16 = fp_round f64Konstantin Zhuravlyov2016-11-171-0/+20
* [AMDGPU] Promote f16/i16 conversions to f32/i32Konstantin Zhuravlyov2016-11-171-52/+8
* [AMDGPU] Expand `br_cc` for f16Konstantin Zhuravlyov2016-11-171-0/+1
* [AMDGPU] Handle f16 select{_cc}Konstantin Zhuravlyov2016-11-161-0/+1
* AMDGPU/SI: Support data types other than V4f32 in image intrinsicsChangpeng Fang2016-11-141-2/+5
* [AMDGPU] Add f16 support (VI+)Konstantin Zhuravlyov2016-11-131-13/+103
* AMDGPU/SI: Promote i16 = fp_[us]int f32 for VITom Stellard2016-11-121-0/+6
* AMDGPU: Add VI i16 supportTom Stellard2016-11-101-4/+72
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