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* [AArch64][SVE] Fold constant multiply of element countCullen Rhodes2019-12-203-1/+54
* [AArch64][SVE] Add intrnisics for saturating scalar arithmeticAndrzej Warzynski2019-12-202-69/+137
* Recommit "[AArch64][SVE] Add permutation and selection intrinsics"Cullen Rhodes2019-12-205-42/+264
* [AArch64][SVE] Add intrinsics for binary narrowing operationsAndrzej Warzynski2019-12-203-22/+59
* [ARM][MVE] Fixes for tail predication.Sam Parker2019-12-203-12/+61
* [ARM][MVE] Tail predicate in the presence of vcmpSam Parker2019-12-203-76/+270
* [ARM][MVE] Tail predicate bottom/top muls.Sam Parker2019-12-201-0/+3
* [X86] Make EmitCmp into a static function and explicitly return chain result ...Craig Topper2019-12-192-18/+19
* [X86] Directly call EmitTest in two places instead of creating a null constan...Craig Topper2019-12-191-4/+2
* [StackMaps] Be explicit about label formation [NFC] (try 2)Philip Reames2019-12-194-9/+43
* Temporarily Revert "[StackMaps] Be explicit about label formation [NFC]"Eric Christopher2019-12-191-14/+3
* [StackMaps] Be explicit about label formation [NFC]Philip Reames2019-12-191-3/+14
* [FaultMaps] Make label formation a bit more explicit [NFC]Philip Reames2019-12-191-1/+5
* [RISCV] Don't crash on unsupported relocationsLuís Marques2019-12-191-2/+11
* [SystemZ] Recognize mrecord-mcount in backendJonas Paulsson2019-12-192-3/+18
* [RISCV] Enable the machine outliner for RISC-Vlewis-revill2019-12-193-0/+190
* [PowerPC] Only use PLT annotations if using PIC relocation modelJustin Hibbits2019-12-191-1/+7
* Revert "[AArch64][SVE] Add permutation and selection intrinsics"Cullen Rhodes2019-12-195-264/+42
* [AArch64][SVE] Add permutation and selection intrinsicsCullen Rhodes2019-12-195-42/+264
* [llvm-exegesis] Fix pfm counter names for Haswell for older versions of libpfmMiloš Stojanović2019-12-191-8/+8
* Make more use of MachineInstr::mayLoadOrStore.Jay Foad2019-12-1910-14/+14
* [ARM] Improve codegen of volatile load/store of i64Victor Campos2019-12-196-6/+158
* [AArch64][SVE] Implement pfirst and pnext intrinsicsCullen Rhodes2019-12-192-5/+12
* [AArch64][SVE] Implement ptrue intrinsicCullen Rhodes2019-12-193-10/+19
* [AMDGPU] Implemented fma cost analysisStanislav Mekhanoshin2019-12-182-0/+53
* Enable STRICT_FP_TO_SINT/UINT on X86 backendLiu, Chen32019-12-195-113/+196
* [PowerPC] make lwa as a valid ds candidate in ppcloopinstrformprep passczhengsz2019-12-181-5/+9
* [WebAssembly] Add avgr_u intrinsics and require nuw in patternsThomas Lively2019-12-181-16/+17
* [X86] Add a simple hack to IsProfitableToFold to prevent vselect+strict fp op...Craig Topper2019-12-181-0/+6
* [FPEnv] Strict versions of llvm.minimum/llvm.maximumUlrich Weigand2019-12-182-2/+4
* Revert "[AArch64][SVE] Replace integer immediate intrinsics with splat vector...Danilo Carvalho Grael2019-12-182-39/+22
* [Clang FE, SystemZ] Don't add "true" value for the "mnop-mcount" attribute.Jonas Paulsson2019-12-182-3/+2
* [PowerPC][NFC] Refactor splat of constant to vector.Stefan Pintilie2019-12-181-25/+4
* [AArch64][SVE] Replace integer immediate intrinsics with splat vector variantDanilo Carvalho Grael2019-12-182-22/+39
* [gicombiner] Import tryCombineIndexedLoadStore()Daniel Sanders2019-12-181-6/+1
* [AArch64] match fcvtl2 with bitcasted extractSanjay Patel2019-12-182-6/+35
* [gicombiner] Add support for arbitrary match data being passed from match to ...Daniel Sanders2019-12-181-14/+12
* [AArch64] Improve codegen of volatile load/store of i128Victor Campos2019-12-183-14/+69
* [AArch64] Enable clustering memory accesses to fixed stack objectsJay Foad2019-12-183-118/+90
* [NFC][TTI] Add Alignment for isLegalMasked[Gather/Scatter]Anna Welker2019-12-183-7/+13
* [X86] Add strict fma supportWang, Pengfei2019-12-184-19/+26
* [PowerPC] Add missing legalization for vector BSWAPNemanja Ivanovic2019-12-174-3/+31
* [X86] Manually format some setOperationAction calls to line up arguments to i...Craig Topper2019-12-171-8/+8
* [AArch64][GlobalISel]: Fix a crash in GlobalIsel in dealing with 16bit uadd.w...Xiaoqing Wu2019-12-171-1/+2
* [AMDGPU] Fixed cost model for packed 16 bit opsStanislav Mekhanoshin2019-12-171-1/+13
* [WebAssembly] Implement SIMD {i8x16,i16x8}.avgr_u instructionsThomas Lively2019-12-171-1/+20
* [AIX] Avoid unset csect assert for functions defined after their use in TOCDavid Tenty2019-12-171-16/+17
* AMDGPU/SILoadStoreOptimillzer: Refactor CombineInfo structTom Stellard2019-12-171-241/+216
* [AMDGPU] Fix typo in SIInstrInfo::memOpsHaveSameBasePtrJay Foad2019-12-171-1/+1
* [RISCV] Add subtargets initialized with target featureZakk Chen2019-12-172-6/+31
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