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| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2017-05-17 19:25:06 +0000 |
|---|---|---|
| committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2017-05-17 19:25:06 +0000 |
| commit | ee324ffc1f8d664e8dd27cab6e50807e90ee0032 (patch) | |
| tree | 5294ced368ece6fe641ba0d842968ffc2ab02635 /llvm/lib/Target/AMDGPU/SIISelLowering.cpp | |
| parent | a9a92a1a6a4820fcb2729d94d13ce26cd693583e (diff) | |
| download | bcm5719-llvm-ee324ffc1f8d664e8dd27cab6e50807e90ee0032.tar.gz bcm5719-llvm-ee324ffc1f8d664e8dd27cab6e50807e90ee0032.zip | |
AMDGPU: Fix min3/max3 combines for f16/i16
Fix missing instruction definitions for min3/max3.
llvm-svn: 303284
Diffstat (limited to 'llvm/lib/Target/AMDGPU/SIISelLowering.cpp')
| -rw-r--r-- | llvm/lib/Target/AMDGPU/SIISelLowering.cpp | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp index 48a14e4dbea..286be355bc1 100644 --- a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp +++ b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp @@ -4491,7 +4491,8 @@ SDValue SITargetLowering::performMinMaxCombine(SDNode *N, if (Opc != AMDGPUISD::FMIN_LEGACY && Opc != AMDGPUISD::FMAX_LEGACY && - VT != MVT::f64) { + VT != MVT::f64 && + ((VT != MVT::f16 && VT != MVT::i16) || Subtarget->hasMin3Max3_16())) { // max(max(a, b), c) -> max3(a, b, c) // min(min(a, b), c) -> min3(a, b, c) if (Op0.getOpcode() == Opc && Op0.hasOneUse()) { |
