summaryrefslogtreecommitdiffstats
path: root/llvm/lib/Target/AMDGPU
Commit message (Expand)AuthorAgeFilesLines
...
* [Alignment][NFC] Remove LogAlignment functionsGuillaume Chatelet2019-09-181-1/+1
* [AMDGPU] Allow FP inline constant in v_madak_f16 and v_fmaak_f16Tim Renouf2019-09-181-1/+3
* [AMDGPU] Added MI bit IsDOTStanislav Mekhanoshin2019-09-176-2/+22
* [SVE][MVT] Fixed-length vector MVT rangesGraham Hunter2019-09-171-1/+1
* [AMDGPU]: PHI Elimination hooks added for custom COPY insertion. FixedAlexander Timofeev2019-09-173-15/+84
* AMDGPU/GlobalISel: Fail select of G_INSERT non-32-bit sourceMatt Arsenault2019-09-161-4/+16
* AMDGPU/GlobalISel: Fix RegBankSelect for G_FRINT and G_FCEILMatt Arsenault2019-09-161-0/+2
* AMDGPU/GlobalISel: Select SMRD loads for more typesMatt Arsenault2019-09-161-3/+12
* AMDGPU/GlobalISel: RegBankSelect for killMatt Arsenault2019-09-161-0/+4
* AMDGPU/GlobalISel: Legalize s1 source G_[SU]ITOFPMatt Arsenault2019-09-161-1/+2
* AMDGPU/GlobalISel: Set type on vgpr live in special argumentsMatt Arsenault2019-09-161-1/+2
* AMDGPU/GlobalISel: Select S16->S32 fptointMatt Arsenault2019-09-162-3/+3
* AMDGPU/GlobalISel: Select s32->s16 G_[US]ITOFPMatt Arsenault2019-09-161-2/+2
* AMDGPU/GlobalISel: Fix VALU s16 fnegMatt Arsenault2019-09-161-0/+10
* Revert for: [AMDGPU]: PHI Elimination hooks added for custom COPY insertion.Alexander Timofeev2019-09-133-50/+5
* [Alignment] Introduce llvm::Align to MCSectionGuillaume Chatelet2019-09-131-1/+1
* AMDGPU/GlobalISel: Fix assert on multi-return side effect intrinsicsMatt Arsenault2019-09-131-1/+1
* AMDGPU/GlobalISel: Legalize s32->s16 G_SITOFP/G_UITOFPMatt Arsenault2019-09-131-1/+1
* AMDGPU/GlobalISel: Fix RegBankSelect for amdgcn.elseMatt Arsenault2019-09-131-0/+7
* AMDGPU/GlobalISel: Select 16-bit VALU bit opsMatt Arsenault2019-09-131-3/+3
* AMDGPU/GlobalISel: Legalize G_FFLOORMatt Arsenault2019-09-132-2/+3
* AMDGPU/GlobalISel: Legalize G_FMADMatt Arsenault2019-09-133-0/+36
* AMDGPU/GlobalISel: Select G_CTPOPMatt Arsenault2019-09-134-2/+15
* DAG/GlobalISel: Correct type profile of bitcount opsMatt Arsenault2019-09-131-1/+1
* AMDGPU: Inline constant when materalizing FI with add on gfx9Matt Arsenault2019-09-122-3/+6
* AMDGPU: Fix bug in r371671 on some builds.Austin Kerbow2019-09-121-2/+5
* AMDGPU: Move m0 initializations earlierAustin Kerbow2019-09-111-4/+38
* [AMDGPU] Fix crash in phi-elimination hook.Michael Liao2019-09-111-2/+4
* [Alignment] Use llvm::Align in MachineFunction and TargetLowering - fixes mir...Guillaume Chatelet2019-09-112-2/+2
* GlobalISel/TableGen: Handle REG_SEQUENCE patternsMatt Arsenault2019-09-101-14/+36
* AMDGPU/GlobalISel: Select G_FABS/G_FNEGMatt Arsenault2019-09-102-52/+92
* AMDGPU/GlobalISel: Select cvt pk intrinsicsMatt Arsenault2019-09-102-14/+25
* AMDGPU/GlobalISel: Select llvm.amdgcn.sffbhMatt Arsenault2019-09-102-2/+6
* AMDGPU/GlobalISel: RegBankSelect for G_ZEXTLOAD/G_SEXTLOADMatt Arsenault2019-09-102-3/+11
* AMDGPU/GlobalISel: Legalize constant 32-bit loadsMatt Arsenault2019-09-102-0/+18
* AMDGPU/GlobalISel: First pass at attempting to legalize load/storesMatt Arsenault2019-09-103-83/+285
* [Alignment][NFC] Use llvm::Align for TargetLowering::getPrefLoopAlignmentGuillaume Chatelet2019-09-102-12/+12
* [AMDGPU]: PHI Elimination hooks added for custom COPY insertion.Alexander Timofeev2019-09-103-5/+48
* AMDGPU/GlobalISel: Fix insert point when lowering fminnum/fmaxnumMatt Arsenault2019-09-091-1/+1
* AMDGPU/GlobalISel: Rename MIRBuilder to B. NFCAustin Kerbow2019-09-094-139/+136
* AMDGPU/GlobalISel: Legalize G_BUILD_VECTOR v2s16Matt Arsenault2019-09-092-34/+64
* AMDGPU: Make VReg_1 size be 1Matt Arsenault2019-09-093-5/+17
* AMDGPU/GlobalISel: Select llvm.amdgcn.classMatt Arsenault2019-09-095-1/+32
* AMDGPU/GlobalISel: Select fmed3Matt Arsenault2019-09-094-1/+37
* AMDGPU: Use PatFrags to allow selecting custom nodes or intrinsicsMatt Arsenault2019-09-091-10/+39
* AMDGPU: Move MnemonicAlias out of instruction def hierarchyMatt Arsenault2019-09-094-30/+19
* AMDGPU/GlobalISel: Implement LDS G_GLOBAL_VALUEMatt Arsenault2019-09-095-1/+48
* AMDGPU/GlobalISel: Legalize G_BUILD_VECTOR_TRUNCMatt Arsenault2019-09-093-0/+70
* AMDGPU/GlobalISel: Select atomic loadsMatt Arsenault2019-09-092-5/+18
* AMDGPU/GlobalISel: Fix RegBankSelect for unaligned, uniform constant loadsMatt Arsenault2019-09-091-4/+5
OpenPOWER on IntegriCloud