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* Fix clang -Wimplicit-fallthrough warnings across llvm, NFCReid Kleckner2018-11-011-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | This patch should not introduce any behavior changes. It consists of mostly one of two changes: 1. Replacing fall through comments with the LLVM_FALLTHROUGH macro 2. Inserting 'break' before falling through into a case block consisting of only 'break'. We were already using this warning with GCC, but its warning behaves slightly differently. In this patch, the following differences are relevant: 1. GCC recognizes comments that say "fall through" as annotations, clang doesn't 2. GCC doesn't warn on "case N: foo(); default: break;", clang does 3. GCC doesn't warn when the case contains a switch, but falls through the outer case. I will enable the warning separately in a follow-up patch so that it can be cleanly reverted if necessary. Reviewers: alexfh, rsmith, lattner, rtrieu, EricWF, bollu Differential Revision: https://reviews.llvm.org/D53950 llvm-svn: 345882
* AMDGPU/GlobalISel: Add support for G_INTTOPTRTom Stellard2018-10-051-0/+1
| | | | | | | | | | | | | | Summary: This is a no-op. Reviewers: arsenm Reviewed By: arsenm Subscribers: kzhuravl, jvesely, wdng, nhaehnle, yaxunl, rovka, kristof.beyls, dstuttard, tpr, t-tye, llvm-commits Differential Revision: https://reviews.llvm.org/D52916 llvm-svn: 343839
* AMDGPU/GlobalISel: Define instruction mapping for G_SELECTTom Stellard2018-09-011-0/+54
| | | | | | | | | | | | Reviewers: arsenm Reviewed By: arsenm Subscribers: kzhuravl, wdng, nhaehnle, yaxunl, rovka, kristof.beyls, dstuttard, tpr, llvm-commits, t-tye Differential Revision: https://reviews.llvm.org/D49737 llvm-svn: 341271
* AMDGPU/GlobalISel: Define instruction mapping for G_INSERTTom Stellard2018-08-111-0/+14
| | | | | | | | | | | | Reviewers: arsenm Reviewed By: arsenm Subscribers: kzhuravl, wdng, nhaehnle, yaxunl, rovka, kristof.beyls, dstuttard, tpr, t-tye, llvm-commits Differential Revision: https://reviews.llvm.org/D49625 llvm-svn: 339491
* AMDGPU/GlobalISel: Add support for llvm.amdgcn.kernarg.segment.ptrMatt Arsenault2018-06-251-1/+6
| | | | | | | | | Note a normal select test is not currently possible because this relies on input registers tracked in SIMachineFunctionInfo which are not currently serializable in MIR, but this does work end-to-end from the IR. llvm-svn: 335490
* AMDGPU: Remove #include "MCTargetDesc/AMDGPUMCTargetDesc.h" from common headersTom Stellard2018-05-221-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | Summary: MCTargetDesc/AMDGPUMCTargetDesc.h contains enums for all the instuction and register defintions, which are huge so we only want to include them where needed. This will also make it easier if we want to split the R600 and GCN definitions into separate tablegenerated files. I was unable to remove AMDGPUMCTargetDesc.h from SIMachineFunctionInfo.h because it uses some enums from the header to initialize default values for the SIMachineFunction class, so I ended up having to remove includes of SIMachineFunctionInfo.h from headers too. Reviewers: arsenm, nhaehnle Reviewed By: nhaehnle Subscribers: MatzeB, kzhuravl, wdng, yaxunl, dstuttard, tpr, t-tye, javed.absar, llvm-commits Differential Revision: https://reviews.llvm.org/D46272 llvm-svn: 332930
* AMDGPU/GlobalISel: RegBankSelect for basic int opsMatt Arsenault2018-03-191-0/+3
| | | | llvm-svn: 327843
* AMDGPU/GlobalISel: Legality and RegBankInfo for G_{INSERT|EXTRACT}_VECTOR_ELTMatt Arsenault2018-03-121-0/+59
| | | | llvm-svn: 327269
* AMDGPU/GlobalISel: InstrMapping for G_MERGE_VALUESMatt Arsenault2018-03-121-0/+12
| | | | llvm-svn: 327268
* AMDGPU/GlobalISel: Add InstrMapping for G_EXTRACTMatt Arsenault2018-03-051-0/+9
| | | | llvm-svn: 326715
* AMDGPU/GlobalISel: InstrMapping for G_ZEXTMatt Arsenault2018-03-021-0/+20
| | | | llvm-svn: 326589
* AMDGPU/GlobalISel: InstrMapping for G_TRUNCMatt Arsenault2018-03-021-0/+10
| | | | llvm-svn: 326588
* AMDGPU/GlobalISel: Define InstrMappings for G_FCMPMatt Arsenault2018-03-021-0/+9
| | | | | | Patch by Tom Stellard llvm-svn: 326587
* AMDGPU/GlobalISel: Define instruction mapping for @llvm.minnumMatt Arsenault2018-03-021-0/+1
| | | | | | Patch by Tom Stellard llvm-svn: 326586
* AMDGPU/GlobalISel: Define instruction mapping for @llvm.maxnumMatt Arsenault2018-03-021-0/+1
| | | | | | Patch by Tom Stellard llvm-svn: 326567
* AMDGPU/GlobalISel: Define instruction mapping for G_FPTOSIMatt Arsenault2018-03-021-0/+1
| | | | | | Patch by Tom Stellard llvm-svn: 326534
* AMDGPU/GlobalISel: Define instruction mapping for G_FPTOUIMatt Arsenault2018-03-021-0/+1
| | | | | | Patch by Tom Stellard llvm-svn: 326533
* AMDGPU/GlobalISel: Define instruction mapping for G_FMULMatt Arsenault2018-03-021-0/+1
| | | | llvm-svn: 326532
* AMDGPU/GlobalISel: Define instruction mapping for G_FADDMatt Arsenault2018-03-021-1/+3
| | | | | | Patch by Tom Stellard llvm-svn: 326526
* AMDGPU/GlobalISel: Define instruction mapping for G_SHLMatt Arsenault2018-03-021-0/+1
| | | | | | Patch by Tom Stellard llvm-svn: 326525
* AMDGPU/GlobalISel: Define instruction mapping for G_XORMatt Arsenault2018-03-021-0/+1
| | | | llvm-svn: 326524
* AMDGPU/GlobalISel: Define instruction mapping for G_ANDMatt Arsenault2018-03-021-0/+1
| | | | | | Patch by Tom Stellard llvm-svn: 326523
* AMDGPU/GlobalISel: Define instruction mapping for @llvm.amdgcn.cvt.pkrtzMatt Arsenault2018-03-011-1/+13
| | | | | | Patch by Tom Stellard llvm-svn: 326490
* AMDGPU/GlobalISel: Define instruction mapping for G_ORMatt Arsenault2018-03-011-0/+54
| | | | | | Patch by Tom Stellard llvm-svn: 326489
* AMDGPU/GlobalISel: Remove default register mappingMatt Arsenault2018-03-011-16/+1
| | | | | | | | | This crashes for some opcodes, which prevents the SelectionDAG fallback from working. Patch by Tom Stellard llvm-svn: 326487
* AMDGPU/GlobalISel: Define instruction mapping for G_BITCASTMatt Arsenault2018-03-011-0/+6
| | | | | | Patch by Tom Stellard llvm-svn: 326482
* AMDGPU/GlobalISel: InstrMapping for llvm.amdgcn.exp.comprMatt Arsenault2018-03-011-4/+16
| | | | | | Patch by Tom Stellard llvm-svn: 326479
* AMDGPU/GlobalISel: Define instruction mapping for @llvm.amdgcn.expMatt Arsenault2018-03-011-1/+21
| | | | | | Patch by Tom Stellard llvm-svn: 326477
* AMDGPU/GlobalISel: Define InstrMappings for G_ICMPMatt Arsenault2018-03-011-1/+74
| | | | | | Patch by Tom Stellard llvm-svn: 326472
* AMDGPU/GlobalISel: Define instruction mapping for G_IMPLICIT_DEFMatt Arsenault2018-03-011-0/+5
| | | | | | Patch by Tom Stellard llvm-svn: 326470
* AMDGPU/GlobalISel: Define instruction mapping for G_FCONSTANTMatt Arsenault2018-03-011-0/+1
| | | | | | Patch by Tom Stellard llvm-svn: 326468
* AMDGPU/GlobalISel: Add copyCost for VGPR->SGPR copiesMatt Arsenault2018-03-011-4/+7
| | | | | | Patch by Tom Stellard llvm-svn: 326467
* AMDGPU: Fix layering issueMatt Arsenault2018-02-091-1/+1
| | | | | | | Move utility function that depends on codegen. Fixes build with r324487 reapplied. llvm-svn: 324746
* Fix a bunch more layering of CodeGen headers that are in TargetDavid Blaikie2017-11-171-2/+2
| | | | | | | | All these headers already depend on CodeGen headers so moving them into CodeGen fixes the layering (since CodeGen depends on Target, not the other way around). llvm-svn: 318490
* [GlobalISel] Make GlobalISel a non-optional library.Quentin Colombet2017-08-031-4/+0
| | | | | | | | With this change, the GlobalISel library gets always built. In particular, this is not possible to opt GlobalISel out of the build using the LLVM_BUILD_GLOBAL_ISEL variable any more. llvm-svn: 309990
* [RegisterBankInfo] Uniquely allocate instruction mapping.Quentin Colombet2017-05-051-45/+46
| | | | | | | | | | This is a step toward having statically allocated instruciton mapping. We are going to tablegen them eventually, so let us reflect that in the API. NFC. llvm-svn: 302316
* AMDGPU: Fix release build broken by r293551Tom Stellard2017-01-301-0/+2
| | | | llvm-svn: 293553
* Re-commit AMDGPU/GlobalISel: Add support for simple shadersTom Stellard2017-01-301-0/+228
| | | | | | | | | | | | | | Fix build when global-isel is disabled and fix a warning. Summary: We can select constant/global G_LOAD, global G_STORE, and G_GEP. Reviewers: qcolombet, MatzeB, t.p.northover, ab, arsenm Subscribers: mehdi_amini, vkalintiris, kzhuravl, wdng, nhaehnle, mgorny, yaxunl, tony-tye, modocache, llvm-commits, dberris Differential Revision: https://reviews.llvm.org/D26730 llvm-svn: 293551
* Revert "AMDGPU/GlobalISel: Add support for simple shaders"Tom Stellard2017-01-301-228/+0
| | | | | | | | This reverts commit r293503. Revert while I investigate some of the buildbot failures. llvm-svn: 293509
* AMDGPU/GlobalISel: Add support for simple shadersTom Stellard2017-01-301-0/+228
Summary: We can select constant/global G_LOAD, global G_STORE, and G_GEP. Reviewers: qcolombet, MatzeB, t.p.northover, ab, arsenm Subscribers: mehdi_amini, vkalintiris, kzhuravl, wdng, nhaehnle, mgorny, yaxunl, tony-tye, modocache, llvm-commits, dberris Differential Revision: https://reviews.llvm.org/D26730 llvm-svn: 293503
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