AMDGPU/GlobalISel: Define instruction mapping for @llvm.amdgcn.cvt.pkrtz

Patch by Tom Stellard

llvm-svn: 326490

1 files changed, 13 insertions, 1 deletions

diff --git a/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp b/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
index 74a4e0b81c7..22f178aa5ee 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
@@ -205,7 +205,10 @@ AMDGPURegisterBankInfo::getDefaultMappingVOP(const MachineInstr &MI) const {
   unsigned Size0 = getSizeInBits(MI.getOperand(0).getReg(), MRI, *TRI);
   OpdsMapping[OpdIdx++] = AMDGPU::getValueMapping(AMDGPU::VGPRRegBankID, Size0);
 
-  unsigned Reg1 = MI.getOperand(1).getReg();
+  if (MI.getOperand(OpdIdx).isIntrinsicID())
+    OpdsMapping[OpdIdx++] = nullptr;
+
+  unsigned Reg1 = MI.getOperand(OpdIdx).getReg();
   unsigned Size1 = getSizeInBits(Reg1, MRI, *TRI);
   unsigned Bank1 = getRegBankID(Reg1, MRI, *TRI);
   OpdsMapping[OpdIdx++] = AMDGPU::getValueMapping(Bank1, Size1);
@@ -344,6 +347,15 @@ AMDGPURegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
     OpdsMapping[3] = AMDGPU::getValueMapping(Op3Bank, Size);
     break;
   }
+  case AMDGPU::G_INTRINSIC: {
+    switch(MI.getOperand(1).getIntrinsicID()) {
+    default:
+      return getInvalidInstructionMapping();
+    case Intrinsic::amdgcn_cvt_pkrtz:
+      return getDefaultMappingVOP(MI);
+    }
+    break;
+  }
   case AMDGPU::G_INTRINSIC_W_SIDE_EFFECTS: {
     switch (MI.getOperand(0).getIntrinsicID()) {
     default: