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| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2018-03-02 01:22:06 +0000 |
|---|---|---|
| committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2018-03-02 01:22:06 +0000 |
| commit | 3c7a123ccc943bb34a022c29ee31470876c01c6a (patch) | |
| tree | 0ab7f21cb7c034653ef50fc20ab406c07305dc53 /llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp | |
| parent | c0f34c9e3665020b32c561c6555eea44d2b6a08f (diff) | |
| download | bcm5719-llvm-3c7a123ccc943bb34a022c29ee31470876c01c6a.tar.gz bcm5719-llvm-3c7a123ccc943bb34a022c29ee31470876c01c6a.zip | |
AMDGPU/GlobalISel: Define instruction mapping for G_XOR
llvm-svn: 326524
Diffstat (limited to 'llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp')
| -rw-r--r-- | llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp b/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp index 8a145bd21ff..558d51da39f 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp @@ -286,6 +286,7 @@ AMDGPURegisterBankInfo::getInstrMapping(const MachineInstr &MI) const { return getInvalidInstructionMapping(); case AMDGPU::G_AND: case AMDGPU::G_OR: + case AMDGPU::G_XOR: if (isSALUMapping(MI)) return getDefaultMappingSOP(MI); return getDefaultMappingVOP(MI); |
