summaryrefslogtreecommitdiffstats
path: root/llvm/lib/CodeGen/SelectionDAG
Commit message (Expand)AuthorAgeFilesLines
...
* [DAG] Add SelectionDAG::MaxRecursionDepth constantSimon Pilgrim2019-09-193-8/+10
* Revert r372285 "GlobalISel: Don't materialize immarg arguments to intrinsics"Hans Wennborg2019-09-191-16/+2
* GlobalISel: Don't materialize immarg arguments to intrinsicsMatt Arsenault2019-09-191-2/+16
* [DAGCombine][ARM][X86] (sub Carry, X) -> (addcarry (sub 0, X), 0, Carry) foldRoman Lebedev2019-09-181-0/+12
* [SimplifyDemandedBits] Use APInt::intersects to instead of ANDing and compari...Craig Topper2019-09-171-2/+3
* [TargetLowering] SimplifyDemandedBits - add EXTRACT_SUBVECTOR support.Simon Pilgrim2019-09-141-0/+15
* [TargetRegisterInfo] Remove SVT argument from getCommonSubClass.Craig Topper2019-09-131-1/+1
* [SDAG] Update generic code to conservatively check for isAtomic in addition t...Philip Reames2019-09-124-49/+80
* [DAGCombiner][X86] Pass the CmpOpVT to reduceSelectOfFPConstantLoads so X86 c...Craig Topper2019-09-121-1/+1
* [SelectionDAGBuilder] Simplify loop in visitSelect back to how it was before ...Craig Topper2019-09-121-2/+1
* [DAGCombine] visitFDIV - Use isCheaperToUseNegatedFPOps helper for (fdiv (fne...Simon Pilgrim2019-09-121-15/+5
* AArch64: support arm64_32, an ILP32 slice for watchOS.Tim Northover2019-09-121-0/+4
* [DAGCombiner] Improve division estimation of floating points.Qiu Chaofan2019-09-121-11/+33
* [LegalizeTypes] Remove code for softening a float type to itself.Craig Topper2019-09-125-266/+58
* [Alignment] Use Align for TargetLowering::MinStackArgumentAlignmentGuillaume Chatelet2019-09-101-7/+6
* [LegalizeTypes] Teach SoftenFloatOp_SELECT_CC to handle operand 2 or 3 being ...Craig Topper2019-09-102-3/+15
* Introduce infrastructure for an incremental port of SelectionDAG atomic load/...Philip Reames2019-09-091-4/+29
* [SelectionDAG] Remove ISD::FP_ROUND_INREGCraig Topper2019-09-096-59/+1
* GlobalISel: add combiner to form indexed loads.Tim Northover2019-09-091-1/+1
* [DAGCombiner][X86][ARM] Teach visitMULO to fold multiplies with 0 to 0 and no...Craig Topper2019-09-081-3/+19
* [CodeGen] Handle SMULFIXSAT with scale zero in TargetLowering::expandFixedPoi...Bjorn Pettersson2019-09-071-10/+21
* [Intrinsic] Add the llvm.umul.fix.sat intrinsicBjorn Pettersson2019-09-078-46/+148
* Change TargetLibraryInfo analysis passes to always require FunctionTeresa Johnson2019-09-071-1/+1
* Update CodeGen to use hasMetadata as appropriate [NFC]Philip Reames2019-09-042-12/+11
* [CodeGen] Use FSHR in DAGTypeLegalizer::ExpandIntRes_MULFIXBjorn Pettersson2019-09-031-49/+19
* [LegalizeDAG] Pass DAG to two calls to SDNode::dump in debug prints so that t...Craig Topper2019-09-031-2/+2
* [DAGCombiner] try to form test+set out of shift+mask patternsSanjay Patel2019-09-021-0/+57
* [DAGCombiner] improve throughput of shift+logic+shiftSanjay Patel2019-09-011-0/+74
* [TargetLowering] Fix Bugzilla ID 43183 to avoid soften comparison broken with...Shiva Chen2019-09-012-45/+88
* [DAGCombiner] clean up code in visitShiftByConstant()Sanjay Patel2019-08-311-25/+20
* [DAGCombiner] Match (add X, X) as (shl X, 1) when detecting rotate.Amaury Sechet2019-08-311-4/+20
* [DAGCombiner] Don't create illegal narrow storesJames Molloy2019-08-311-2/+7
* [CodeGen] Refactor DAGTypeLegalizer::ExpandIntRes_MULFIX. NFCBjorn Pettersson2019-08-311-87/+92
* [DAGCombine] ReduceLoadWidth - remove duplicate SDLoc. NFCI.Simon Pilgrim2019-08-301-3/+2
* [TargetLowering] SimplifyDemandedBits ADD/SUB/MUL - correctly inherit SDNodeF...Simon Pilgrim2019-08-301-4/+2
* [DAGCombine] visitVSELECT - remove equivalent getValueType() call. NFCI.Simon Pilgrim2019-08-301-1/+0
* [DAGCombine] visitVSELECT - remove duplicate getOperand calls. NFCI.Simon Pilgrim2019-08-301-4/+3
* [DAGCombine] visitVSELECT - use getShiftAmountTy for shift amounts.Simon Pilgrim2019-08-301-3/+3
* [DAGCombine] visitMULHS - use getScalarValueSizeInBits() to make safe for vec...Simon Pilgrim2019-08-301-1/+1
* [DAGCombine] visitMULHS/visitMULHU - isBuildVectorAllZeros doesn't mean node ...Simon Pilgrim2019-08-301-8/+8
* [CodeGen] Fix lowering for returning the result of an extractvalueDan Gohman2019-08-301-1/+1
* [DAGCombine] Fix shadow variable warnings. NFCI.Simon Pilgrim2019-08-291-12/+12
* Fix signed/unsigned comparison warning. NFCI.Simon Pilgrim2019-08-291-1/+2
* Fix shadow variable warning. NFCI.Simon Pilgrim2019-08-291-4/+3
* [DAGCombiner] (insert_vector_elt (vector_shuffle X, Y), (extract_vector_elt X...Amaury Sechet2019-08-291-4/+43
* LegalizeSetCCCondCode - Reduce scope of NeedSwap to fix cppcheck warning. NFCI.Simon Pilgrim2019-08-291-1/+1
* [X86] Make inline assembly 'x' and 'v' constraints work for f128.Craig Topper2019-08-291-2/+6
* [RISCV] Avoid generating AssertZext for LP64 ABI when lowering floating LibCallShiva Chen2019-08-282-8/+66
* [FPEnv] Add fptosi and fptoui constrained intrinsics.Kevin P. Neal2019-08-289-14/+139
* [DAGCombine] Fix cppcheck shadow variable warning. NFCI.Simon Pilgrim2019-08-281-4/+4
OpenPOWER on IntegriCloud