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path: root/llvm/lib/CodeGen/SelectionDAG
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* [DAGCombine] Check the uses of negated floating constant and remove the hackQingShan Zhang2020-06-261-11/+15
* [LegalizeTypes][RISCV] Correctly sign-extend comparison for ATOMIC_CMP_XCHGAlex Bradbury2020-06-251-1/+13
* [DAGCombine] Fix splitting indexed loads in ForwardStoreValueToDirectLoad()Nemanja Ivanovic2020-04-141-10/+15
* [CodeGen] Fix sinking local values in lpads with phisReid Kleckner2020-04-131-1/+16
* No longer generate calls to *_finiteserge-sans-paille2020-02-281-61/+12
* [Codegen] Revert rL354676/rL354677 and followups - introduced PR43446 miscompileRoman Lebedev2020-02-261-27/+0
* [AArch64][FPenv] Update chain of int to fp conversionDiogo Sampaio2020-02-181-2/+8
* Revert "[DebugInfo] Remove some users of DBG_VALUEs IsIndirect field"Jeremy Morse2020-02-123-19/+16
* Revert "[DebugInfo][DAG] Distinguish different kinds of location indirection"Jeremy Morse2020-02-121-19/+5
* [ARM][VecReduce] Force expand vector_reduce_fminDavid Green2020-02-051-2/+2
* [DAGCombine] Replace `getIntPtrConstant()` with `getVectorIdxTy()`.Michael Liao2020-01-141-1/+2
* [LegalizeTypes] Remove untested code from ExpandIntOp_UINT_TO_FPCraig Topper2020-01-141-70/+2
* [FPEnv] Fix chain handling regression after 04a8696Ulrich Weigand2020-01-142-34/+31
* [SelectionDAG] ComputeKnownBits - merge getValidMinimumShiftAmountConstant() ...Simon Pilgrim2020-01-141-11/+12
* [SelectionDAG] ComputeKnownBits - merge getValidMinimumShiftAmountConstant() ...Simon Pilgrim2020-01-141-10/+12
* [LegalizeIntegerTypes][X86] Add support for expanding input of STRICT_SINT_TO...Craig Topper2020-01-131-6/+30
* Rework be15dfa88fb1 such that it works with GlobalISel which doesn't use EVTDaniel Sanders2020-01-131-3/+11
* [SelectionDAG] ComputeNumSignBits add getValidMaximumShiftAmountConstant() fo...Simon Pilgrim2020-01-131-0/+31
* [LegalizeTypes] Add SoftenFloatResult support for STRICT_SINT_TO_FP/STRICT_UI...Andrew Wei2020-01-141-8/+16
* [SelectionDAG] ComputeNumSignBits add getValidMinimumShiftAmountConstant() IS...Simon Pilgrim2020-01-131-1/+4
* [SelectionDAG] ComputeNumSignBits - Use getValidShiftAmountConstant for shift...Simon Pilgrim2020-01-131-15/+8
* [SelectionDAG] ComputeKnownBits - Add DemandedElts support to getValidShiftAm...Simon Pilgrim2020-01-131-8/+14
* [FPEnv] Fix chain handling for fpexcept.strict nodesUlrich Weigand2020-01-132-14/+81
* [SelectionDAG] ComputeKnownBits add getValidMinimumShiftAmountConstant() ISD:...Simon Pilgrim2020-01-131-0/+3
* [SelectionDAG] ComputeKnownBits - minimum leading/trailing zero bits in LSHR/...Simon Pilgrim2020-01-131-0/+11
* [LegalizeVectorOps] Parallelize the lo/hi part of STRICT_UINT_TO_FLOAT legali...Craig Topper2020-01-111-3/+6
* [TargetLowering][X86] Connect the chain from STRICT_FSETCC in TargetLowering:...Craig Topper2020-01-111-3/+5
* [LegalizeVectorOps] Expand vector MERGE_VALUES immediately.Craig Topper2020-01-111-0/+11
* [LegalizeVectorOps] Remove some of the simpler Expand methods. Pass Results v...Craig Topper2020-01-111-125/+77
* [LegalizeVectorOps] Only pass SDNode* instead SDValue to all of the Expand* a...Craig Topper2020-01-111-251/+251
* [TargetLowering][ARM][Mips][WebAssembly] Remove the ordered FP compare from R...Craig Topper2020-01-101-5/+3
* [TargetLowering] Use SelectionDAG::getSetCC and remove a repeated call to get...Craig Topper2020-01-101-8/+4
* [TargetLowering][ARM][X86] Change softenSetCCOperands handling of ONE to avoi...Craig Topper2020-01-101-10/+9
* [LegalizeVectorOps] Improve handling of multi-result operations.Craig Topper2020-01-101-173/+271
* [FPEnv] Invert sense of MIFlag::FPExcept flagUlrich Weigand2020-01-101-2/+2
* [MIR] Fix cyclic dependency of MIR formatterPeng Guo2020-01-101-2/+1
* DAG: Don't use unchecked dyn_castMatt Arsenault2020-01-091-4/+4
* CodeGen: Use LLT instead of EVT in getRegisterByNameMatt Arsenault2020-01-091-3/+9
* [TargetLowering][X86] TeachSimplifyDemandedBits to handle cases where only th...Craig Topper2020-01-091-0/+21
* [DAGCombiner] reduce extract subvector of concatSanjay Patel2020-01-091-2/+16
* [DAGCombine] Fold the (fma -x, y, -z) to -(fma x, y, z)QingShan Zhang2020-01-091-0/+9
* Revert "Revert "[MIR] Target specific MIR formating and parsing""Daniel Sanders2020-01-081-1/+2
* Revert "[MIR] Target specific MIR formating and parsing"Nico Weber2020-01-081-1/+1
* [MIR] Target specific MIR formating and parsingPeng Guo2020-01-081-1/+1
* Revert "[MIR] Target specific MIR formating and parsing"Daniel Sanders2020-01-081-1/+1
* [MIR] Target specific MIR formating and parsingPeng Guo2020-01-081-1/+1
* [SelectionDAG] Use llvm::Optional<APInt> for FoldValue.Simon Pilgrim2020-01-081-32/+30
* [DAGCombiner] clean up extract-of-concat fold; NFCSanjay Patel2020-01-081-13/+21
* [Intrinsic] Add fixed point division intrinsics.Bevin Hansson2020-01-088-23/+283
* [X86] Adding fp128 support for strict fcmpWang, Pengfei2020-01-082-20/+58
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