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path: root/llvm/lib/CodeGen/SelectionDAG
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* Introduce TLI predicative for base-relative Jump Tables.Joerg Sonnenberger2016-11-151-1/+1
* DAGCombiner: fix combine of trunc and selectAsaf Badouh2016-11-151-1/+1
* [SelectionDAG] Add support for vector demandedelts in BSWAP opcodesSimon Pilgrim2016-11-111-1/+2
* [SelectionDAG] Add support for vector demandedelts in UREM/SREM opcodesSimon Pilgrim2016-11-111-6/+10
* [SelectionDAG] Add support for vector demandedelts in UDIV opcodesSimon Pilgrim2016-11-111-2/+4
* [DAG Combiner] Fix the native computation of the Newton series for reciprocalsEvandro Menezes2016-11-101-28/+30
* [SelectionDAG] Add support for vector demandedelts in ADD/SUB opcodesSimon Pilgrim2016-11-101-3/+6
* [SelectionDAG] Add support for splatted vectors in SUB opcodeSimon Pilgrim2016-11-101-1/+1
* [SelectionDAG] Add support for vector demandedelts in TRUNCATE opcodesSimon Pilgrim2016-11-101-1/+2
* Use common SDLoc. NFCI.Simon Pilgrim2016-11-101-3/+3
* [SelectionDAG] Add support for vector demandedelts in MUL opcodesSimon Pilgrim2016-11-101-3/+5
* [SelectionDAG] Add support for vector demandedelts in SRA opcodesSimon Pilgrim2016-11-101-1/+2
* [DAGCombiner] Correctly extract the ConstOrConstSplat shift value for SHL nodesSimon Pilgrim2016-11-101-3/+2
* [SelectionDAG] Add support for vector demandedelts in SHL/SRL opcodesSimon Pilgrim2016-11-101-2/+4
* [TargetLowering] Fix undef vector element issue with true/false result handlingSimon Pilgrim2016-11-081-10/+10
* [VectorLegalizer] Expansion of CTLZ using CTPOP when possibleSimon Pilgrim2016-11-081-6/+50
* Add -O0 support for @llvm.invariant.group.barrier by discarding it if it gets...Richard Smith2016-11-072-0/+2
* [SelectionDAG] Add support for vector demandedelts in XOR opcodesSimon Pilgrim2016-11-061-2/+4
* [SelectionDAG] Add support for vector demandedelts in OR opcodesSimon Pilgrim2016-11-061-2/+4
* DAGCombiner: fix use-after-free when merging consecutive storesNicolai Haehnle2016-11-031-18/+22
* Expandload and Compressstore intrinsicsElena Demikhovsky2016-11-034-22/+72
* Use !operator to test if APInt is zero/non-zero. NFCI.Simon Pilgrim2016-11-021-3/+3
* Simplify.Joerg Sonnenberger2016-11-021-2/+2
* [DAG] disable nsw/nuw for add/sub/mul when simplifying based on demanded bits...Sanjay Patel2016-10-311-7/+18
* [DAG] x | x --> xSanjay Patel2016-10-301-0/+4
* [DAG] x & x --> xSanjay Patel2016-10-301-0/+4
* [DAGCombiner] (REAPPLIED) Add vector demanded elements support to computeKnow...Simon Pilgrim2016-10-291-13/+111
* [DAGCombiner] Fix a crash visiting `AND` nodes.Davide Italiano2016-10-281-1/+6
* SDAG: Make sure we use an allocatable reg class when we create this vregJustin Bogner2016-10-281-0/+2
* [SelectionDAG] computeKnownBits - early-out if any BUILD_VECTOR element has n...Simon Pilgrim2016-10-281-0/+4
* [SelectionDAG] Tidyup UDIV computeKnownBits implementationSimon Pilgrim2016-10-281-2/+0
* [SelectionDAG] Increment computeKnownBits recursion depth for SMIN/SMAX/UMIN/...Simon Pilgrim2016-10-281-2/+2
* Revert "[DAGCombiner] Add vector demanded elements support to computeKnownBits"Juergen Ributzka2016-10-281-111/+13
* [DAGCombiner] Add vector demanded elements support to computeKnownBitsSimon Pilgrim2016-10-271-13/+111
* Do not assume that FP vector operands are never legalized by expandingNemanja Ivanovic2016-10-261-1/+2
* LegalizeDAG: Support promoting [US]DIV and [US]REM operationsTom Stellard2016-10-261-1/+18
* [DAGCombiner] Enable (urem x, (shl pow2, y)) -> (and x, (add (shl pow2, y), -...Simon Pilgrim2016-10-251-3/+3
* [DAGCombiner] Enable srem(x.y) -> urem(x,y) combine for vectorsSimon Pilgrim2016-10-251-4/+2
* [DAGCombiner] Enable sdiv(x.y) -> udiv(x,y) combine for vectorsSimon Pilgrim2016-10-251-4/+2
* Switch lowering: improve partitioning of jump tablesEvandro Menezes2016-10-251-14/+31
* [DAGCombine] Preserve shuffles when one of the vector operands is constantZvi Rackover2016-10-251-34/+75
* [SelectionDAG] Update ComputeNumSignBits SRA/SHL handlers to accept scalar or...Simon Pilgrim2016-10-241-6/+7
* Use SDValue::getConstantOperandVal() helper. NFCI.Simon Pilgrim2016-10-241-4/+2
* CodeGen: Do not add a global's address space to the folding set profile.Peter Collingbourne2016-10-241-2/+0
* [DAG] enhance computeKnownBits to handle SRL/SRA with vector splat constantSanjay Patel2016-10-231-43/+32
* Use SDValue::getConstantOperandVal() helper. NFCI.Simon Pilgrim2016-10-231-4/+1
* [DAG] enhance computeKnownBits to handle SHL with vector splat constantSanjay Patel2016-10-211-10/+9
* [DAG] fold negation of sign-bitSanjay Patel2016-10-211-11/+27
* [DAG] use SDNode flags 'nsz' to enable fadd/fsub with zero foldsSanjay Patel2016-10-211-16/+20
* Fix *_EXTEND_VECTOR_INREG legalizationPirama Arumuga Nainar2016-10-201-3/+19
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