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| author | Simon Pilgrim <llvm-dev@redking.me.uk> | 2016-11-06 16:29:09 +0000 |
|---|---|---|
| committer | Simon Pilgrim <llvm-dev@redking.me.uk> | 2016-11-06 16:29:09 +0000 |
| commit | dd4809a6036f19e5e54d97af090911d2dcf21a0f (patch) | |
| tree | 912132d5df8f469ea1b8421082f85f7283845015 /llvm/lib/CodeGen/SelectionDAG | |
| parent | c9467ed31ed4a48309c51a4bdac114970d26eeaf (diff) | |
| download | bcm5719-llvm-dd4809a6036f19e5e54d97af090911d2dcf21a0f.tar.gz bcm5719-llvm-dd4809a6036f19e5e54d97af090911d2dcf21a0f.zip | |
[SelectionDAG] Add support for vector demandedelts in OR opcodes
llvm-svn: 286071
Diffstat (limited to 'llvm/lib/CodeGen/SelectionDAG')
| -rw-r--r-- | llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp index 98cd8190815..430f39d9b52 100644 --- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp @@ -2142,8 +2142,10 @@ void SelectionDAG::computeKnownBits(SDValue Op, APInt &KnownZero, KnownZero |= KnownZero2; break; case ISD::OR: - computeKnownBits(Op.getOperand(1), KnownZero, KnownOne, Depth+1); - computeKnownBits(Op.getOperand(0), KnownZero2, KnownOne2, Depth+1); + computeKnownBits(Op.getOperand(1), KnownZero, KnownOne, DemandedElts, + Depth + 1); + computeKnownBits(Op.getOperand(0), KnownZero2, KnownOne2, DemandedElts, + Depth + 1); // Output known-0 bits are only known if clear in both the LHS & RHS. KnownZero &= KnownZero2; |
