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| author | Simon Pilgrim <llvm-dev@redking.me.uk> | 2016-11-10 15:05:09 +0000 |
|---|---|---|
| committer | Simon Pilgrim <llvm-dev@redking.me.uk> | 2016-11-10 15:05:09 +0000 |
| commit | ca57e53ded1f0c0d697c99c1d8442c2dce011d0c (patch) | |
| tree | f42742083ea44ed8863445bcb2f3c67509e08d41 /llvm/lib/CodeGen/SelectionDAG | |
| parent | 40d33e75542f3a8a281cb180f2e72cbea0539ff8 (diff) | |
| download | bcm5719-llvm-ca57e53ded1f0c0d697c99c1d8442c2dce011d0c.tar.gz bcm5719-llvm-ca57e53ded1f0c0d697c99c1d8442c2dce011d0c.zip | |
[SelectionDAG] Add support for vector demandedelts in SRA opcodes
llvm-svn: 286461
Diffstat (limited to 'llvm/lib/CodeGen/SelectionDAG')
| -rw-r--r-- | llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp index 6d25ead3fe3..e272315d826 100644 --- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp @@ -2265,7 +2265,8 @@ void SelectionDAG::computeKnownBits(SDValue Op, APInt &KnownZero, break; case ISD::SRA: if (const APInt *ShAmt = getValidShiftAmountConstant(Op)) { - computeKnownBits(Op.getOperand(0), KnownZero, KnownOne, Depth + 1); + computeKnownBits(Op.getOperand(0), KnownZero, KnownOne, DemandedElts, + Depth + 1); KnownZero = KnownZero.lshr(*ShAmt); KnownOne = KnownOne.lshr(*ShAmt); // If we know the value of the sign bit, then we know it is copied across |
