summaryrefslogtreecommitdiffstats
path: root/llvm/lib
Commit message (Expand)AuthorAgeFilesLines
* Revert "[JumpThreading] Unfold selects that depend on the same condition"Pablo Barrio2016-11-151-77/+38
* Revert "[JumpThreading] Prevent non-deterministic use lists"Pablo Barrio2016-11-151-7/+8
* [ARM] Make sure GlobalISel is only initialized once. NFCIDiana Picus2016-11-151-12/+12
* [LoopVectorizer] When estimating reg usage, unused insts may "end" another useRobert Lougher2016-11-151-3/+4
* [PowerPC] Implement BE VSX load/store builtins - llvm portion.Tony Jiang2016-11-152-0/+15
* Get GlobalISel to build on Linux after r286407Diana Picus2016-11-151-1/+1
* [X86][FastISel] Assert that we are dealing with arithmetic with overflow intr...Zvi Rackover2016-11-151-0/+3
* [AMDGPU] TableGen: change individual instruction flags to bit type from bits<1>Sam Kolton2016-11-153-47/+47
* [X86][FastISel] Fix lowering of overflow result on AVX512 targetsZvi Rackover2016-11-151-2/+2
* Test commit, remove trailing space.Florian Hahn2016-11-151-1/+1
* Introduce TLI predicative for base-relative Jump Tables.Joerg Sonnenberger2016-11-153-38/+6
* [ARM] Add machine scheduler for Cortex-R52 Javed Absar2016-11-153-1/+985
* DAGCombiner: fix combine of trunc and selectAsaf Badouh2016-11-151-1/+1
* TableGen: Add operator !orMatt Arsenault2016-11-154-2/+9
* [X86][GlobalISel] Add minimal call lowering support to the IRTranslatorZvi Rackover2016-11-157-2/+196
* [X86] Add LLVM version number for each intrinsic handled by auto upgrade for ...Craig Topper2016-11-151-152/+158
* AMDGPU: Fix f16 fabs/fnegMatt Arsenault2016-11-152-4/+18
* Simplify identify_magic.Rui Ueyama2016-11-151-26/+23
* Improve DWARF parsing speed by improving DWARFAbbreviationDeclarationGreg Clayton2016-11-153-36/+132
* Fix -Wswitch.Rui Ueyama2016-11-152-0/+2
* Add a file magic for CL.exe's object file created with /GL.Rui Ueyama2016-11-152-11/+8
* AMDGPU: Set hasExtraSrcRegAllocReq on v_div_scale_*Matt Arsenault2016-11-151-0/+2
* AMDGPU: Fix formatting of 1/2pi immediateMatt Arsenault2016-11-151-2/+2
* MIRParser: Add support for parsing vreg reg alloc hintsTom Stellard2016-11-153-2/+30
* [AArch64] Compute the Newton series for reciprocals nativelyEvandro Menezes2016-11-143-6/+75
* Linker: Remove unnecessary call to copyMetadata in IRLinker::linkGlobalVariable.Peter Collingbourne2016-11-141-2/+0
* RegAllocGreedy: Properly initialize this pass, so that -run-pass will workTom Stellard2016-11-142-13/+19
* [tsan] Add support for C++ exceptions into TSan (call __tsan_func_exit during...Kuba Brecka2016-11-147-178/+195
* Add a checkSymbolTable() method to the MachOObjectFile class.Kevin Enderby2016-11-141-0/+68
* [Hexagon] Give a predicate function a more meaningful nameKrzysztof Parzyszek2016-11-142-18/+18
* ARM: try to fix GCC 4.8 compilation again after r286881.Tim Northover2016-11-141-1/+2
* Recommit: ARM: sort register lists by encoding in push/pop instructions.Tim Northover2016-11-143-2/+28
* [AArch64] Change some pointers to references. NFC.Geoff Berry2016-11-141-16/+16
* [AArch64] Split 0 vector stores into scalar store pairs.Geoff Berry2016-11-141-4/+67
* [AArch64] Factor out transform code from split16BStore. NFC.Geoff Berry2016-11-141-24/+31
* [ThinLTO] Only promote exported locals as marked in indexTeresa Johnson2016-11-143-16/+44
* [libFuzzer] replace 'auto' with 'auto *' to better follow the LLVM styleKostya Serebryany2016-11-141-3/+3
* Revert: r286868 - Test commitDaniel Sanders2016-11-141-1/+0
* Test commitDaniel Sanders2016-11-141-0/+1
* Revert "ARM: sort register lists by encoding in push/pop instructions."Tim Northover2016-11-143-28/+2
* ARM: sort register lists by encoding in push/pop instructions.Tim Northover2016-11-143-2/+28
* [PPC] Add intrinsic mapping to the xscvhpsp instructionSean Fertile2016-11-141-0/+9
* AMDGPU/SI: Support data types other than V4f32 in image intrinsicsChangpeng Fang2016-11-142-63/+73
* Use _Unwind_Backtrace on Apple platforms.Bob Wilson2016-11-141-1/+1
* TypoAdrian Prantl2016-11-141-1/+1
* Restore "[ThinLTO] Prevent exporting of locals used/defined in module level asm"Teresa Johnson2016-11-144-9/+64
* [Hexagon] Remove unsafe load instructions that affect Stack Slot ColoringSumanth Gundapaneni2016-11-141-12/+0
* [ThinLTO] Make inline assembly handling more efficient in summaryTeresa Johnson2016-11-144-9/+20
* [CostModel][X86] Added mul costs for vXi8 vectorsSimon Pilgrim2016-11-141-5/+21
* [X86][AVX] Fixed v16i16/v32i8 ADD/SUB costs on AVX1 subtargetsSimon Pilgrim2016-11-141-0/+4
OpenPOWER on IntegriCloud