summaryrefslogtreecommitdiffstats
path: root/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
Commit message (Expand)AuthorAgeFilesLines
...
* Speculatively disable Dan's commits 143177 and 143179 to see ifDuncan Sands2011-10-281-134/+0
* Eliminate LegalizeOps' LegalizedNodes map and have it just call RAUWDan Gohman2011-10-281-0/+134
* Change this overloaded use of Sched::Latency to be an overloadedDan Gohman2011-10-241-4/+4
* Remove a now dead function, fixing -Wunused-function warnings fromChandler Carruth2011-10-211-20/+0
* Delete the list-tdrr scheduler. Top-down schedulers are going awayDan Gohman2011-10-201-203/+11
* PreRA scheduler should avoid cloning compares.Andrew Trick2011-09-011-1/+35
* - Rename TargetInstrDesc, TargetOperandInfo to MCInstrDesc and MCOperandInfo andEvan Cheng2011-06-281-20/+20
* More refactoring. Move getRegClass from TargetOperandInfo to TargetInstrInfo.Evan Cheng2011-06-271-1/+1
* pre-RA-sched: Cleanup register pressure tracking.Andrew Trick2011-06-271-7/+3
* Distinguish early clobber output operands from clobbered registers.Jakob Stoklund Olesen2011-06-271-1/+2
* Fix some trailing issues from my introduction of MVT::untyped and its use for...Owen Anderson2011-06-211-1/+11
* Remove unused but set variables.Benjamin Kramer2011-06-181-2/+0
* Add a new MVT::untyped. This will be used in future work for modelling ISA f...Owen Anderson2011-06-151-9/+39
* Added -stress-sched flag in the Asserts build.Andrew Trick2011-06-151-14/+42
* Remove a temporary test case probe in CheckForLiveRegDef.Andrew Trick2011-06-081-1/+0
* Fix a merge bug in preRAsched for handling physreg aliases.Andrew Trick2011-06-071-4/+6
* Be careful about scheduling nodes above previous calls. It increase usages ofEvan Cheng2011-04-261-1/+42
* Fix typoEvan Cheng2011-04-261-1/+1
* In the pre-RA scheduler, maintain cmp+br proximity.Andrew Trick2011-04-141-13/+53
* Recommit r129383. PreRA scheduler heuristic fixes: VRegCycle, TokenFactor lat...Andrew Trick2011-04-131-110/+176
* Revert 129383. It causes some targets to hit a scheduler assert.Andrew Trick2011-04-121-177/+111
* PreRA scheduler heuristic fixes: VRegCycle, TokenFactor latency.Andrew Trick2011-04-121-111/+177
* Added a check in the preRA scheduler for potential interference on aAndrew Trick2011-04-071-4/+55
* Fix for -pre-RA-sched=source.Andrew Trick2011-03-251-0/+2
* Ensure that def-side physreg copies are scheduled above any other usesAndrew Trick2011-03-231-0/+9
* whitespaceAndrew Trick2011-03-231-2/+2
* Grammar-o.Eric Christopher2011-03-211-1/+1
* Re-commit 127368 and 127371. They are exonerated.Evan Cheng2011-03-101-5/+11
* Revert 127368 and 127371 for now.Evan Cheng2011-03-091-11/+5
* Change the definition of TargetRegisterInfo::getCrossCopyRegClass to be moreEvan Cheng2011-03-091-5/+11
* Fix typo, make helper static.Benjamin Kramer2011-03-091-3/+3
* Fix some latent bugs if the nodes are unschedulable. We'd gotten awayEric Christopher2011-03-081-1/+6
* Further improvements to pre-RA-sched=list-ilp.Andrew Trick2011-03-081-17/+62
* Move getRegPressureLimit() from TargetLoweringInfo to TargetRegisterInfo.Cameron Zwarich2011-03-071-1/+1
* Typo.Eric Christopher2011-03-061-1/+1
* Disable a couple of experimental heuristics to get the best results from the ...Andrew Trick2011-03-061-2/+2
* Be explicit with abs(). Visual Studio workaround.Andrew Trick2011-03-051-4/+6
* Missing comment.Andrew Trick2011-03-051-0/+2
* Increased the register pressure limit on x86_64 from 8 to 12Andrew Trick2011-03-051-22/+143
* Minor pre-RA-sched fixes and cleanup.Andrew Trick2011-03-041-7/+15
* Introducing a new method of tracking register pressure. We can'tAndrew Trick2011-02-041-111/+62
* Remove a temporary workaround for a lencod miscompile. Depends on the fix in ...Andrew Trick2011-01-271-2/+0
* Temporarily workaround JM/lencod miscompile (SIGSEGV).Andrew Trick2011-01-241-0/+2
* Enable support for precise scheduling of the instruction selectionAndrew Trick2011-01-211-1/+1
* Convert -enable-sched-cycles and -enable-sched-hazard to -disableAndrew Trick2011-01-211-29/+31
* Selection DAG scheduler register pressure heuristic fixes.Andrew Trick2011-01-201-8/+27
* Support for precise scheduling of the instruction selection DAG,Andrew Trick2011-01-141-537/+663
* Minor cleanup related to my latest scheduler changes.Andrew Trick2010-12-241-3/+5
* Fix a few cases where the scheduler is not checking for phys reg copies. The ...Andrew Trick2010-12-241-3/+10
* Various bits of framework needed for precise machine-level selectionAndrew Trick2010-12-241-60/+367
OpenPOWER on IntegriCloud